Methods for fabricating integrated circuits

1. A method for fabricating an integrated circuit comprising:

forming a first layer of a first semiconductor material overlying a bulk semiconductor substrate that is formed of a second semiconductor material;

forming a second layer of a third semiconductor material overlying the first layer;

etching a first plurality of trenches into the first and second layers;

filling the first plurality of trenches with a structure forming material to form a plurality of support structures;

etching a second plurality of trenches into the first and second layers, wherein portions of the second layer disposed between adjacent trenches of the first and second plurality of trenches define a plurality of fins;

etching the first layer to form gap spaces between the bulk semiconductor substrate and the plurality of fins, wherein the plurality of fins are supported in position adjacent to the gap spaces by the plurality of support structures; and

filling the gap spaces with an insulating material.

2. The method of claim 1 , wherein forming the first layer comprises providing the bulk semiconductor substrate of the second semiconductor material that comprises silicon.

3. The method of claim 1 , wherein forming the first layer comprises forming the first layer of the first semiconductor material that comprises silicon germanium.

4. The method of claim 1 , wherein forming the second layer comprises forming the second layer of the third semiconductor material that comprises silicon.

5. The method of claim 1 , wherein etching the first plurality of trenches comprises etching through the first and second layers into the bulk semiconductor substrate to form the first plurality of trenches.

6. The method of claim 1 , wherein filling the first plurality of trenches comprises forming the plurality of support structures coupled to the bulk semiconductor substrate.

7. The method of claim 1 , wherein filling the first plurality of trenches comprises filling the first plurality of trenches with the structure forming material that comprises an oxide material.

8. The method of claim 1 , wherein etching the second plurality of trenches comprises etching through the first and second layers into the bulk semiconductor substrate to form the second plurality of trenches.

9. The method of claim 1 , wherein filling the gap spaces comprises filling the gap spaces with the insulating material that comprises silicon oxide.

10. The method of claim 1 , wherein filling the gap spaces comprises filling the second plurality of trenches with the insulating material.

11. The method of claim 10 , further comprising:

removing portions of the insulating material and the plurality of support structures to expose the plurality of fins.

12. The method of claim 1 , further comprising:

forming at least one hard mask layer of a hard mask material overlying the second layer; and

forming a sacrificial layer of a fourth semiconductor material overlying the at least one hard mask layer, and wherein etching the first plurality of trenches comprises etching through the sacrificial layer and the at least one hard mask layer and into the first and second layers to form the first plurality of trenches.

13. The method of claim 12 , further comprising:

etching the sacrificial layer to expose upper portions of the plurality of support structures; and

forming sidewall spacers on the upper portions of the plurality of support structures, and wherein etching the second plurality of trenches comprises etching the second plurality of trenches using the plurality of support structures and the sidewall spacers as an etch mask.

14. The method of claim 12 , wherein forming the sacrificial layer comprises forming the sacrificial layer of the fourth semiconductor material that comprises amorphous carbon.

15. A method for fabricating an integrated circuit comprising:

forming a first layer of a first semiconductor material overlying a bulk semiconductor substrate that is formed of a second semiconductor material;

forming a second layer of a third semiconductor material overlying the first layer;

etching a first plurality of trenches through the first and second layers into the bulk semiconductor substrate;

filling the first plurality of trenches with a structure forming material to form a plurality of support structures extending from the bulk semiconductor substrate through the first and second layers;

etching a second plurality of trenches through the first and second layers into the bulk semiconductor substrate, wherein the second plurality of trenches are arranged alternately with the first plurality of trenches, and wherein portions of the second layer disposed between adjacent trenches of the first and second plurality of trenches define a plurality of fins;

etching the first layer to form gap spaces between the bulk semiconductor substrate and the plurality of fins, wherein the plurality of fins are supported in position adjacent to the gap spaces by the plurality of support structures; and

filling the gap spaces with an insulating material.

16. The method of claim 15 , further comprising:

forming shallow trench isolation interposed between the plurality of fins.

17. The method of claim 16 , wherein filling the gap spaces comprises filling the second plurality of trenches with the insulating material, and wherein the method further comprises:

removing portions of the insulating material and the plurality of support structures to expose the plurality of fins prior to forming the shallow trench isolation.

18. The method of claim 15 , wherein forming the shallow trench isolation comprises:

forming a dummy oxide layer overlying the plurality of fins subsequent to removing the portions of the insulating material and the plurality of support structures;

forming a hard mask layer overlying the dummy oxide layer;

etching a STI trench through the hard mask and dummy oxide layers into the bulk semiconductor substrate; and

depositing an STI fill material into the STI trench.

19. The method of claim 18 , further comprising:

removing the hard mask layer; and

forming a gate structure overlying at least one of the plurality of fins.

20. A method for fabricating an integrated circuits comprising:

epitaxially growing a first layer of silicon germanium overlying a bulk silicon substrate;

epitaxially growing a second layer of silicon overlying the first layer;

etching a first plurality of trenches through the first and second layers into the bulk silicon substrate;

filling the first plurality of trenches with a first oxide material to form a plurality of support structures extending from the bulk silicon substrate through the first and second layers;

etching a second plurality of trenches through the first and second layers into the bulk silicon substrate, wherein the second plurality of trenches are arranged alternately with the first plurality of trenches, and wherein portions of the second layer disposed between adjacent trenches of the first and second plurality of trenches define a plurality of fins;

etching the first layer to form gap spaces between the bulk silicon substrate and the plurality of fins, wherein the plurality of fins are supported in position adjacent to the gap spaces by the plurality of support structures; and

filling the gap spaces with a second oxide material.