Method for forming N-shaped bottom stress liner
Semiconductor devices with n-shaped bottom stress liners are formed. Embodiments include forming a protuberance on a substrate, conformally forming a sacrificial material layer over the protuberance, forming a gate stack above the sacrificial material layer on a silicon layer, removing the sacrificial material layer to form a tunnel, and forming a stress liner in the tunnel conforming to the shape of the protuberance. Embodiments further include forming a silicon layer over the sacrificial material layer and lining the tunnel with a passivation layer prior to forming the stress liner.
1. A method comprising:
forming a protuberance on a substrate;
conformally forming a sacrificial material layer over the protuberance;
forming a gate stack above the sacrificial material layer on a silicon layer;
removing the sacrificial material layer, forming a tunnel; and
forming a stress liner in the tunnel conforming to the shape of the protuberance.
2. The method according to claim 1 , further comprising:
forming the silicon layer above the sacrificial material layer prior to forming the gate stack, a surface of the silicon layer nearest the sacrificial material layer conforming to the shape of the protuberance.
3. The method according to claim 2 , further comprising:
forming the gate stack according to a gate first process flow and forming source/drain regions embedded within the silicon layer after forming the gate stack, or forming the gate stack according to a gate last process flow and forming source/drain regions embedded within the silicon layer prior to forming the gate stack.
4. The method according to claim 2 , further comprising:
forming raised source/drain regions on the silicon layer subsequent to forming the stress liner.
5. The method according to claim 1 , further comprising:
conformally lining the tunnel with a passivation layer prior to forming the stress liner.
6. The method according to claim 1 , further comprising:
etching the substrate to form the protuberance.
7. The method according to claim 1 , further comprising:
conformally forming an additional stress liner over the gate stack and the substrate.
8. The method according to claim 1 , further comprising:
forming the sacrificial material layer between a pair of shallow trench isolation (STI) structures;
removing a portion of each STI structure, exposing edges of the sacrificial material layer; and
removing the sacrificial material layer according to a self-aligned process.
9. The method according to claim 1 , further comprising:
forming the sacrificial material layer by epitaxially growing silicon germanium (SiGe) over the protuberance.
10. The method according to claim 1 , further comprising:
aligning the gate stack with the protuberance.
11. A method comprising:
etching a silicon substrate to form a protuberance on the silicon substrate;
epitaxially growing a silicon germanium (SiGe) layer over the protuberance;
forming a silicon layer above the SiGe layer, a surface of the silicon layer contiguous with the SiGe layer conforming to the shape of the protuberance;
forming source/drain regions above or embedded within the silicon layer;
forming a gate stack above the protuberance on the silicon layer;
removing the SiGe layer, forming a tunnel; and
forming a stress liner in the tunnel conforming to the shape of the protuberance.
12. The method according to claim 11 , further comprising:
conformally lining the tunnel with a passivation layer prior to forming the stress liner; and
conformally forming an additional stress liner over the gate stack and the substrate.