High-K transistors with low threshold voltage
View Patent ↗A method for forming a semiconductor structure is disclosed. The method includes forming a high-k dielectric layer over a semiconductor substrate and forming a gate layer over the high-k dielectric layer. The method also includes heating the gate layer to 350° C., wherein, if the gate layer includes non-conductive material, the non-conductive material becomes conductive. The method further includes annealing the substrate, the high-k dielectric layer, and the gate layer in excess of 350° C. and, during the annealing, applying a negative electrical bias to the gate layer relative to the semiconductor substrate. A semiconductor structure is also disclosed. The semiconductor structure includes a high-k dielectric layer over a semiconductor substrate, and a gate layer over the high-k dielectric layer. The gate layer has a negative electrical bias during anneal. A p-channel FET including this semiconductor structure is also disclosed.
1. A method for forming a semiconductor structure, the method comprising:
forming a high-k dielectric layer over a semiconductor substrate;
forming a gate layer over the high-k dielectric layer;
patterning the high-k dielectric layer and gate layer to form a plurality of devices on the substrate;
forming an insulating layer electrically isolating the plurality of devices from each other;
forming a metal layer over the insulating layer electrically connecting certain of the plurality of devices to each other; and
applying a negative voltage across the metal layer and the substrate during an anneal in excess of 350° C. to simultaneously create a negative electrical bias across the gate layer of each of the certain plurality of devices.
2. The method of claim 1 , wherein:
the plurality of devices on the substrate are p-channel FETs and n-channel FETs; and
the insulating layer electrically isolates the metal layer from the n-channel FETs, such that the negative electrical bias is only present across the gate layer of each of the p-channel FETs.
3. The method of claim 1 , wherein the metal layer is a sacrificial layer.
4. A method for inhibiting formation of oxygen vacancies in a high-k dielectric layer disposed subjacent to one or more gate stacks of a wafer, the method comprising:
bringing a first electrode into contact with a front side of a wafer;
bringing a second electrode into contact with a back side of the wafer;
annealing the wafer at a temperature in excess of 350° C.; and
during the annealing, applying a negative electrical bias to one or more gate stacks, relative to a substrate region of the wafer via the electrodes.
5. The method of claim 4 , wherein the first and second electrodes are each substantially ring-shaped.