Methods of forming isolation structures on FinFET semiconductor devices

1. A method of forming isolation structures for a FinFET device, comprising:

performing at least one etching process on a semiconducting substrate to form a plurality of trenches and a plurality of fins for said FinFET device in said substrate;

forming an isolation layer in said trenches, said isolation layer having an upper surface that is below an upper surface of said substrate;

forming a layer of insulating material above said isolation layer, said layer of insulating material having an upper surface that is below said upper surface of said substrate; and

forming a gate structure above said isolation layer.

2. The method of claim 1 , wherein said layer of insulating material is comprised of silicon dioxide and said isolation layer is comprised of silicon nitride.

3. The method of claim 1 , wherein forming said isolation layer comprises performing a directional deposition process to form said isolation layer.

4. The method of claim 1 , wherein said directional deposition process is a gas cluster ion beam process.

5. The method of claim 4 , wherein said gas cluster ion beam process is performed at about room temperature and at an energy level ranging from about 5-60 keV using SiH 4 and N 2 clusters.

6. The method of claim 1 , wherein forming said layer of insulating material comprises:

depositing said layer of insulating material above said isolation layer and so as to overfill said trenches;

performing a chemical mechanical polishing process on said deposited layer of insulating material; and

performing an etching process on said layer of insulating material such that, when the etching process is completed, its upper surface is below said upper surface of said substrate.

7. The method of claim 1 , wherein said layer of insulating material is comprised of silicon dioxide and said isolation layer is comprised of a material that is resistant to etching with hydrofluoric acid.

8. A method of forming isolation structures for a FinFET device, comprising:

performing at least one etching process on a semiconducting substrate to form a plurality of trenches and a plurality of fins for said FinFET device in said substrate;

forming a first layer of insulating material in said trenches, said first layer of insulating material having an upper surface that is below an upper surface of said substrate;

forming an isolation layer within said trenches above said first layer of insulating material, said isolation layer having an upper surface that is below said upper surface of said substrate;

forming a second layer of insulating material above said isolation layer, said second layer of insulating material having an upper surface that is below said upper surface of said substrate; and

forming a gate structure above said second layer of insulating material.

9. The method of claim 8 , wherein said first and second layers of insulating material are comprised of silicon dioxide and said isolation layer is comprised of a material that is resistant to etching with hydrofluoric acid.

10. The method of claim 9 , wherein said isolation layer is comprised of silicon nitride.

11. The method of claim 8 , wherein forming said first layer of insulating in said trenches comprises:

depositing said first layer of insulating material so as to overfill said trenches;

performing a chemical mechanical polishing process on said deposited first layer of insulating material; and

performing an etching process on said first layer of insulating material such that, when the etching process is completed, its upper surface is below said upper surface of said substrate.

12. The method of claim 8 , wherein forming said isolation layer comprises performing a directional deposition process to form said isolation layer.

13. The method of claim 12 , wherein said directional deposition process is a gas cluster ion beam process.

14. The method of claim 13 , wherein said gas cluster ion beam process is performed at about room temperature and at an energy level ranging from about 5-60 keV using SiH 4 and N 2 clusters.

15. The method of claim 8 , wherein said isolation layer is a layer of insulating material.

16. The method of claim 8 , wherein forming said second layer of insulating material in said trenches comprises:

depositing said second layer of insulating material above said isolation layer and so as to overfill said trenches;

performing a chemical mechanical polishing process on said deposited second layer of insulating material; and

performing an etching process on said second layer of insulating material such that, when the etching process is completed, its upper surface is below said upper surface of said substrate.

17. The method of claim 8 , wherein said first layer of insulating material has a thickness that falls within the range of 10-70 nm, said isolation layer has a thickness that falls within the range of 5-30 nm and said second layer of insulating material has a thickness that falls within the range of 10-20 nm.

18. The method of claim 8 , wherein said isolation layer acts as an etch stop layer that prevents the loss of said first layer of insulating material during a subsequent etching process.

19. The method of claim 18 , wherein said isolation layer acts as an etch stop layer that prevents the loss of said first layer of insulating material during an etching process performed to form conductive contacts proximate said gate structure.