Method of forming MIM capacitor structure in FEOL

1. A method comprising:

providing a semiconductor substrate;

forming a first capacitor plate over the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer;

depositing a capacitor dielectric layer over the first capacitor plate and the semiconductor structure;

patterning the capacitor dielectric layer to expose a first portion of an upper surface of the first capacitor plate and selected portions of the semiconductor substrate,

wherein the patterning of the capacitor dielectric layer includes leaving a region of the capacitor dielectric layer extending beyond the surrounding spacer and contacting the semiconductor structure;

forming a silicide layer in the first portion and the exposed selected portions;

depositing an interlayer dielectric (ILD);

forming a contact in the ILD, the contact contacting the silicide layer in the first region;

forming a second capacitor plate over the capacitor dielectric layer over at least the first capacitor plate, the second capacitor extending laterally beyond the surrounding spacer and contacting the region of the capacitor dielectric layer,

the second capacitor plate including one of:

a metal plate formed in the ILD and including an upper surface in direct contact with a lower surface of a first metal layer, or

a metal plate formed in the ILD that constitutes part of the first metal layer.

2. The method of claim 1 , further comprising:

forming a dielectric filled trench isolation in an upper surface of the semiconductor substrate prior to forming the first capacitor plate, and wherein the first capacitor plate is positioned on and within the boundaries of the trench isolation.

3. The method of claim 1 , wherein the capacitor dielectric layer includes silicon nitride (Si 3 N 4 ).

4. The method of claim 1 , wherein the second capacitor plate forming and the contact forming are performed without using an etch stop layer.

5. The method of claim 1 , further comprising depositing an etch stop layer over the capacitor dielectric layer and the silicide layer, the second capacitor plate forming and the contact forming including selectively etching through the etch stop layer to the capacitor dielectric layer.

6. The method of claim 1 , wherein the second capacitor plate forming and the contact forming include:

etching a contact opening and a second capacitor plate opening in the ILD, the etching being selective to the capacitor dielectric layer; and

performing a reactive preclean.

7. The method of claim 6 , wherein in the case that the second capacitor plate includes the metal plate formed in the ILD and the upper surface in direct contact with the lower surface of the first metal layer, the second capacitor plate forming and the contact forming include:

depositing a metal in the contact opening and the second capacitor plate opening; and

planarizing the metal prior to forming the first metal layer.

8. The method of claim 6 , wherein in the case that the second capacitor plate includes the metal plate in the ILD that constitutes part of the first metal layer, the second capacitor plate forming includes:

depositing a metal in the second capacitor plate opening; and

patterning the metal to form the second capacitor plate as part of the first metal layer.

9. A method comprising:

providing a semiconductor substrate;

forming a first capacitor plate over the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer;

depositing a capacitor dielectric layer over the first capacitor plate and the semiconductor structure;

patterning the capacitor dielectric layer to expose a first portion of an upper surface of the first capacitor plate and selected portions of the semiconductor substrate;

forming a silicide layer in the first portion and the exposed selected portions;

depositing an etch stop layer over the capacitor dielectric layer and the silicide layer;

depositing an interlayer dielectric (ILD);

forming a contact in the ILD, the contact contacting the silicide layer in the first region, wherein the forming of the contact includes selectively etching through the etch stop layer to the capacitor dielectric layer;

forming a second capacitor plate over the capacitor dielectric layer over at least the first capacitor plate, the second capacitor plate including one of:

a metal plate formed in the ILD and including an upper surface in direct contact with a lower surface of a first metal layer, or

a metal plate formed in the ILD that constitutes part of the first metal layer,

wherein the forming of the second capacitor plate includes selectively etching through the etch stop layer to the capacitor dielectric layer.

10. The method of claim 9 , further comprising:

forming a dielectric filled trench isolation in an upper surface of the semiconductor substrate prior to forming the first capacitor plate, and

wherein the first capacitor plate is positioned on and within the boundaries of the trench isolation.

11. The method of claim 9 , wherein the capacitor dielectric layer includes silicon nitride (Si 3 N 4 ).

12. The method of claim 9 , wherein the capacitor dielectric layer patterning includes leaving a region of the capacitor dielectric layer extending beyond the surrounding spacer and contacting the semiconductor structure, and the second capacitor plate forming includes forming the second capacitor plate to extend laterally beyond the surrounding spacer and contact the region of the capacitor dielectric layer.

13. The method of claim 9 , wherein the second capacitor plate forming and the contact forming are performed without using an etch stop layer.

14. The method of claim 9 , further comprising depositing an etch stop layer over the capacitor dielectric layer and the silicide layer, the second capacitor plate forming and the contact forming including selectively etching through the etch stop layer to the capacitor dielectric layer.

15. The method of claim 9 , wherein in the case that the second capacitor plate includes the metal plate formed in the ILD and the upper surface in direct contact with the lower surface of the first metal layer, the second capacitor plate forming and the contact forming include:

depositing a metal in the contact opening and the second capacitor plate opening; and

planarizing the metal prior to forming the first metal layer.

16. The method of claim 9 , wherein in the case that the second capacitor plate includes the metal plate in the ILD that constitutes part of the first metal layer, the second capacitor plate forming includes:

depositing a metal in the second capacitor plate opening; and

patterning the metal to form the second capacitor plate as part of the first metal layer.

17. A method comprising:

forming a dielectric filled trench isolation in an upper surface of a semiconductor substrate;

forming a first capacitor plate over the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer,

wherein the first capacitor plate is positioned directly in contact with the trench isolation and positioned within the boundaries of the trench isolation;

depositing a capacitor dielectric layer over the first capacitor plate and the semiconductor structure;

patterning the capacitor dielectric layer to expose a first portion of an upper surface of the first capacitor plate and selected portions of the semiconductor substrate;

forming a silicide layer in the first portion and the exposed selected portions;

depositing an interlayer dielectric (ILD)

forming a contact in the ILD, the contact contacting the silicide layer in the first region;

forming a second capacitor plate over the capacitor dielectric layer over at least the first capacitor plate, the second capacitor plate including one of:

a metal plate formed in the ILD and including an upper surface in direct contact with a lower surface of a first metal layer, or

a metal plate formed in the ILD that constitutes part of the first metal layer.