Program processing device and program processing method which is able to control writing into an internal memory

1. A first program processing device connected to a second program processing device provided externally to the first program processing device, comprising:

a CPU structured to carry out predetermined processing according to a program;

an internal memory structured to store the program and data generated by the CPU by carrying out the program, and

a data acquiring circuit structured to acquire the program from a program memory to write into the internal memory before the CPU is activated;

a control terminal connected to the data acquiring circuit structured to control whether or not to activate the data acquiring circuit based on a signal supplied from the outside of the first program processing device;

a debug processing circuit structured to monitor at least one variable contained in the program to carry out a process in accordance with a result obtained in monitoring;

wherein the signal provided from outside of the first program processing device is directly input to the data acquiring circuit without being input to the CPU;

the data acquiring circuit is structured to write the program into the internal memory after the signal supplied from the outside is inputted in the control terminal and when the CPU is not yet executing any instructions;

wherein the CPU is initialized and the program processing device activates the data acquiring circuit to load the program over a data transmission line and subsequently activates the initialized CPU in response to a first state of the control terminal, and subsequently initializes the CPU without activating the data acquiring circuit and activates the subsequently initialized CPU in response to a second state of the control terminal; and

wherein the CPU, the internal memory, the data acquiring circuit, and the debug processing circuit are integrally mounted on a same semiconductor substrate.

2. The first program processing device according to claim 1 , further comprising:

an input/output interface connected to the second program processing device, structured to carry out data transmission for the second program processing device in a predetermined data transmission mode according to the program being carried out, wherein

the data acquiring circuit is structured to acquire the program from the program memory in the same predetermined data transmission mode as that of the input/output interface.

3. The first program processing device according to claim 1 , further comprising a debug interface connected to a debug tool for monitoring a result of processing carried out by the debug processing circuit, for exchanging serial data between the first program processing device and the debug tool.

4. A circuit forming a first program processing device comprising:

a CPU structured to carry out predetermined processing according to a program;

an internal memory structured to store the program and data generated by the CPU by carrying out the program;

a debug processing circuit structured to monitor at least one variable contained in the program to carry out a process in accordance with a result obtained in monitoring;

a data acquiring circuit having an input for receiving a control signal to selectively acquire the program from a data transmission line and to write the program into the internal memory; and

wherein the CPU is initialized and the first program processing device activates the data acquiring circuit to load the program over the data transmission line and subsequently activates the initialized CPU in response to a first state of the control signal, and subsequently initializes the CPU without activating the data acquiring circuit and activates the subsequently initialized CPU in response to a second state of the control signal.

5. The circuit of claim 4 wherein:

the first program processing device further comprises a control terminal for receiving the control signal.

6. The circuit of claim 5 wherein:

the CPU, the internal memory, the debug processing circuit, the data acquiring circuit, and the control terminal are integrally mounted on a same semiconductor substrate.

7. The circuit of claim 4 , further comprising:

an input/output interface connected to the CPU and structured to be connected to the data transmission line.

8. The circuit of claim 7 , wherein input/output interface and the data acquiring circuit are structured to communicate over the data transmission line using a predetermined data transmission mode.

9. The circuit of claim 4 , wherein the CPU and the data acquiring circuit are separately connected to the internal memory.

10. The circuit of claim 4 , wherein the internal memory is a RAM.

11. The circuit of claim 4 , further comprising:

a second program processing device connected to the data transmission line; and

a program memory connected to the second program processing device,

wherein the data acquiring circuit loads the program stored in the program memory from the second program processing device over the data transmission line.

12. The circuit of claim 4 , further comprising:

a debug interface structured to exchange data between the debug processing circuit and a personal computer over a debug communication line.

13. The circuit of claim 12 , wherein the personal computer contains a debug tool.

14. The circuit of claim 4 , wherein the CPU and the debug processing circuit are connected to the internal memory using an internal bus.

15. A method for use in a first program processing device having a CPU and a debug processing circuit comprising:

initializing the CPU;

receiving a control signal;

in response to a first state of the control signal:

loading a program over a data transmission line;

storing the program in an internal memory; and

subsequently activating the initialized CPU;

subsequently initializing the CPU;

in response to a second state of the control signal:

activating the subsequently initialized CPU while skipping acquisition of the program over the data transmission line; and

carrying out predetermined processing by the CPU according to the program while monitoring at least one variable contained in the program using the debug processing circuit.

16. The method of claim 15 further comprising:

modifying the program in the internal memory using the debug processing circuit.

17. The method of claim 16 further comprising, after the modifying:

receiving the control signal in the second state;

initializing the CPU;

activating the CPU while skipping acquisition of the program over the data transmission line; and

carrying out predetermined processing by the CPU according to the program so modified.

18. The method of claim 15 wherein the receiving the control signal comprises:

receiving the control signal supplied from outside of the program processing device on a control terminal.

19. The method of claim 15 wherein the loading the program over the transmission line comprises:

loading a program from a second program processing device.

20. The method of claim 19 wherein the loading the program from the second program processing device comprises:

loading the program into the second program processing device from a program memory; and

providing the program so loaded to the first program processing device.