Implementing semiconductor soc with metal via gate node high performance stacked transistors
A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.
1. A back-end-of-line (BEOL) structure for implementing stacked vertical transistors comprising:
a pair of stacked vertical field effect transistors (FETs) including a series connected N-channel field effect transistor (NFET) and a P-channel field effect transistor (PFET) being formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire;
a channel length of each of said pair of stacked vertical FETs being delineated by said polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; said sequential source deposition, channel deposition and drain deposition of said N-channel FET (NFET) including a sequential deposition of an N+ doped polysilicon defining a N source, a P− doped polysilicon defining a N body, and an N+ doped polysilicon defining a N drain; and said sequential source deposition, channel deposition and drain deposition of said P-channel FET (PFET) including a sequential deposition of a P+ doped polysilicon defining a P source, an N− doped polysilicon defining a P body, and a P+ doped polysilicon defining a P drain;
an ohmic contact deposited on said NFET N+ doped polysilicon drain deposition; and
a wire via being formed defining a gate node of each of said pair of stacked vertical FETs includes forming an etched hole through said source deposition, channel deposition and drain deposition of said NFET and said PFET, and said ohmic contact, and a dielectric layer to a signal wire in the BEOL stack; a thin dielectric deposited in said etched opening, and said thin dielectric removed from a bottom of said etched opening, and a metal deposited in said etched opening.
2. The back-end-of-line (BEOL) structure as recited in claim 1 wherein said wire via being formed defining a gate node provides an electrical input signal connection to each of said pair of stacked vertical field effect transistors (FETs).
3. The back-end-of-line (BEOL) structure as recited in claim 1 wherein said pair of stacked vertical field effect transistors (FETs) includes a stacked N-channel field effect transistor (NFET) and a P-channel field effect transistor (PFET).
4. The back-end-of-line (BEOL) structure as recited in claim 1 includes an output via defining an output connection to each of the pair of stacked vertical FETs.
5. The back-end-of-line (BEOL) structure as recited in claim 1 wherein said sequential source deposition, channel deposition and drain deposition of said NFET and said PFET has a respective thickness of approximately 0.1 μm, 0.05 μm, and 0.1 μm.
6. The back-end-of-line (BEOL) structure as recited in claim 1 includes a wire via formed for defining an output via connected to a common connection of said series connected NFET and said PFET.
7. A pair of stacked vertical field effect transistors (FETs) fabricated in a back-end-of-line (BEOL) structure comprising:
the stacked vertical field effect transistors (FETs) including a series connected N-channel field effect transistor (NFET) and a P-channel field effect transistor (PFET) being formed by a plurality of polycrystalline depositions in a stack between planes of a respective global signal routing wire;
a channel length of each of said pair of stacked vertical FETs being delineated by said polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; said sequential source deposition, channel deposition and drain deposition of said N-channel FET (NFET) including a sequential deposition of an N+ doped polysilicon defining a N source, a P− doped polysilicon defining a N body, and an N+ doped polysilicon defining a N drain; and said sequential source deposition, channel deposition and drain deposition of said P-channel FET (PFET) including a sequential deposition of a P+ doped polysilicon defining a P source, an N− doped polysilicon defining a P body, and a P+ doped polysilicon defining a P drain;
an ohmic contact deposited on said NFET N+ doped polysilicon drain deposition; and
a wire via formed defining a gate node of each of said pair of stacked vertical FETs includes forming an etched hole through said source deposition, channel deposition and drain deposition of said NFET and said PFET, and said ohmic contact, and a dielectric layer to a signal wire in the BEOL stack; a thin dielectric deposited in said etched opening, and said thin dielectric removed from a bottom of said etched opening, and a metal deposited in said etched opening.
8. The pair of stacked vertical field effect transistors (FETs) as recited in claim 7 includes a wire output via connected to a common connection of said series connected NFET and said PFET.