Germanium photodetector schottky contact for integration with CMOS and Si nanophotonics

1. A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device comprising:

depositing a dielectric stack over the photodetector device, wherein the dielectric stack encapsulates the photodetector;

etching an opening into the dielectric stack down to an upper surface of a region of an active area of the photodetector;

depositing, via the opening, a first metal layer directly onto the upper surface of the region of the active area, the first metal layer covering the region of the active area;

forming, within a same mask level, a plurality of contacts including a second metal layer, the second metal layer located on the first metal layer and on at least one contact area corresponding to the CMOS device;

wherein the first metal layer isolates the active area from an occurrence of metal intermixing between the second metal layer and the active area of the photodetector, wherein forming the plurality of contacts comprises:

depositing an oxide layer over the photodetector device and the CMOS device, wherein the oxide layer fills the opening;

etching a first opening into a first region of the oxide layer, wherein the first opening extends into the opening of the dielectric stack down to at least an upper surface of the first metal layer;

etching at least one second opening into a second region of the oxide layer, wherein the second opening extends down to at least an upper surface of the at least one contact area corresponding to the CMOS device;

depositing the second metal layer as a first liner within the first and the second opening;

depositing a third metal layer as a second liner over the first liner within the first and the second opening; and

depositing a metal fill over the second liner within both the first and the second opening, wherein the metal fill substantially fills the first and the second opening.

2. The method of claim 1 , wherein the first metal layer forms a metal-germanium Schottky contact with the region of the active area.

3. The method of claim 1 , wherein the first metal layer comprises a first metal material corresponding to one of the group consisting of titanium nitride, tantalum nitride, pulse nucleation layer tungsten, and physical vapor deposition tungsten.

4. The method of claim 1 , wherein the contacts comprise silicide contact areas corresponding to a CMOS FET transistor device.

5. The method of claim 1 , wherein the first liner comprises a titanium liner.

6. The method of claim 5 , wherein the second liner comprises a titanium nitride liner.

7. The method of claim 6 , wherein the metal fill comprises a tungsten material.

8. The method of claim 1 , further comprising:

implanting, following the etching of the opening, an implant into the region of the active area, wherein the implant modifies Schottky barrier height between the first metal layer and the region of the active area coupled to the first metal layer.

9. The method of claim 8 , wherein the active region comprises a germanium material.

10. The method of claim 9 , wherein the implant comprises at least one of the group consisting of phosphorous (P), nitrogen (N), arsenic (As), antimony (Sb), sulfur (S), boron (B), and indium (In).

11. The method of claim 1 , wherein depositing the first metal layer comprises forming a metal contact liner that extends from within the opening in the dielectric stack to an upper surface region of the dielectric stack adjacent the opening.