Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

1. An electrical junction comprising an interface layer disposed between a contact metal and a group IV semiconductor, the semiconductor comprising a source or drain of a transistor, the interface layer comprising a metal oxide and configured to reduce a height of a Schottky barrier between the contact metal and the semiconductor from that which would exist at a contact junction between the contact metal and the semiconductor without the interface layer disposed therebetween, and wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

2. The electrical junction of claim 1 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.

3. The electrical junction of claim 1 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .

4. The electrical junction of claim 3 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.

5. An electrical junction comprising an interface layer disposed between a contact metal and a semiconductor, the semiconductor comprising a source or drain of a transistor, the interface layer being a metal oxide and sufficiently thick to depin a Fermi level of the semiconductor, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

6. The electrical junction of claim 5 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.

7. The electrical junction of claim 5 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .

8. The electrical junction of claim 7 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.

9. An electrical junction, comprising a conductor; a semiconductor selected from a list consisting of Si, Ge, C (a crystal structure of which is selected from a list comprising a diamond lattice, a fulleride or a polymer), an alloy of Ge and Si, an alloy of Ge and C, an alloy of Si and C, and an alloy of Si, Ge, and C; and an interface layer disposed therebetween, the semiconductor comprising a source or drain of a transistor, the interface layer comprising a metal oxide and being sufficiently thick to approximately equal a penetration depth of metal induced gap states (MIGS) in the semiconductor which would be present the interface layer were absent, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

10. The electrical junction of claim 9 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.

11. The electrical junction of claim 9 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .

12. The electrical junction of claim 11 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.

13. An electrical junction, comprising a semiconductor and a conductor separated from the semiconductor by an interface layer comprising a metal oxide and having a thickness sufficient to depin a Fermi level of the conductor in a vicinity of the junction yet thin enough to provide the junction with a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 , wherein the semiconductor comprises a source or drain of a transistor.

14. The electrical junction of claim 13 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.

15. The electrical junction of claim 13 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .

16. The electrical junction of claim 15 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.

17. An electrical junction comprising an interface layer disposed between a contact metal and a group IV semiconductor, the semiconductor comprising a channel region of a transistor, the interface layer comprising a metal oxide and configured to reduce a height of a Schottky barrier between the contact metal and the semiconductor from that which would exist at a contact junction between the contact metal and the semiconductor without the interface layer disposed therebetween, and wherein the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .

18. An electrical junction comprising an interface layer disposed between a contact metal and a semiconductor, the semiconductor comprising a channel region of a transistor, the interface layer being a metal oxide and sufficiently thick to depin a Fermi level of the semiconductor, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

19. An electrical junction, comprising a conductor; a semiconductor selected from a list consisting of Si, Ge, C (a crystal structure of which is selected from a list comprising a diamond lattice, a fulleride or a polymer), an alloy of Ge and Si, an alloy of Ge and C, an alloy of Si and C, and an alloy of Si, Ge, and C; and an interface layer disposed therebetween, the semiconductor comprising a channel region of a transistor, the interface layer comprising a metal oxide and being sufficiently thick to approximately equal a penetration depth of metal induced gap states (MIGS) in the semiconductor which would be present the interface layer were absent, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .

20. An electrical junction, comprising a semiconductor and a conductor separated from the semiconductor by an interface layer comprising a metal oxide and having a thickness sufficient to depin a Fermi level of the conductor in a vicinity of the junction yet thin enough to provide the junction with a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 , wherein the semiconductor comprises a channel region of a transistor.

21. An electrical junction comprising an interface layer disposed between a contact metal and a group IV semiconductor, the interface layer comprising TiO2 and configured to reduce a height of a Schottky barrier between the contact metal and the semiconductor from that which would exist at a contact junction between the contact metal and the semiconductor without the interface layer disposed therebetween, and wherein the electrical junction has a specific contact resistance of less than or equal to approximately 1000 Ω-μm 2 .

22. The electrical junction of claim 21 , wherein the contact metal is a metal or a stack of metals deposited on the TiO 2 .

23. The electrical junction of claim 21 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

24. The electrical junction of claim 21 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm 2 .

25. The electrical junction of claim 24 , wherein the contact metal is a metal or a stack of metals deposited on the TiO2.

26. The electrical junction of claim 24 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

27. The electrical junction of claim 21 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

28. The electrical junction of claim 27 , wherein the contact metal is a metal or a stack of metals deposited on the TiO2.

29. The electrical junction of claim 27 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

30. The electrical junction of claim 27 , wherein the semiconductor comprises an n-type doped group IV semiconductor and comprises a source or drain of a transistor.

31. The electrical junction of claim 21 , wherein the semiconductor comprises an n-type doped group IV semiconductor and comprises a source or drain of a transistor, and the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .

32. An electrical junction comprising an interface layer disposed between a contact metal and a semiconductor, the interface layer being TiO2 and sufficiently thick to depin a Fermi level of the semiconductor, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-μm 2 .

33. The electrical junction of claim 32 , wherein the contact metal is a metal or a stack of metals deposited on the TiO2.

34. The electrical junction of claim 32 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

35. The electrical junction of claim 32 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm 2 .

36. The electrical junction of claim 35 , wherein the contact metal is a metal or a stack of metals deposited on the TiO2.

37. The electrical junction of claim 35 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

38. The electrical junction of claim 32 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

39. The electrical junction of claim 38 , wherein the contact metal is a metal or a stack of metals deposited on the TiO2.

40. The electrical junction of claim 38 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

41. The electrical junction of claim 38 , wherein the semiconductor comprises an n-type doped group IV semiconductor and comprises a source or drain of a transistor.

42. The electrical junction of claim 32 , wherein the semiconductor comprises an n-type doped group IV semiconductor and comprises a source or drain of a transistor, and the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .

43. An electrical junction, comprising a conductor; a semiconductor selected from a list consisting of Si, Ge, C (a crystal structure of which is selected from a list comprising a diamond lattice, a fulleride or a polymer), an alloy of Ge and Si, an alloy of Ge and C, an alloy of Si and C, and an alloy of Si, Ge, and C; and an interface layer disposed therebetween, the interface layer comprising TiO2 and being sufficiently thick to approximately equal a penetration depth of metal induced gap states (MIGS) in the semiconductor which would be present the interface layer were absent, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-μm 2 .

44. The electrical junction of claim 43 , wherein the contact metal is a metal or a stack of metals deposited on the TiO2.

45. The electrical junction of claim 43 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

46. The electrical junction of claim 43 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm 2 .

47. The electrical junction of claim 46 , wherein the contact metal is a metal or a stack of metals deposited on the TiO2.

48. The electrical junction of claim 46 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

49. The electrical junction of claim 43 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

50. The electrical junction of claim 49 , wherein the contact metal is a metal or a stack of metals deposited on the TiO2.

51. The electrical junction of claim 49 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

52. The electrical junction of claim 49 , wherein the semiconductor comprises an n-type doped group IV semiconductor and comprises a source or drain of a transistor.

53. The electrical junction of claim 43 , wherein the semiconductor comprises an n-type doped group IV semiconductor and comprises a source or drain of a transistor, and the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .

54. An electrical junction, comprising a semiconductor and a conductor separated from the semiconductor by an interface layer comprising TiO2 and having a thickness sufficient to depin a Fermi level of the conductor in a vicinity of the junction yet thin enough to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-μm 2 .

55. The electrical junction of claim 54 , wherein the contact metal is a metal or a stack of metals deposited on the TiO2.

56. The electrical junction of claim 54 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

57. The electrical junction of claim 54 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm 2 .

58. The electrical junction of claim 57 , wherein the contact metal is a metal or a stack of metals deposited on the TiO2.

59. The electrical junction of claim 57 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

60. The electrical junction of claim 54 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

61. The electrical junction of claim 60 , wherein the contact metal is a metal or a stack of metals deposited on the TiO2.

62. The electrical junction of claim 60 , wherein the semiconductor comprises an n-type doped group IV semiconductor.

63. The electrical junction of claim 60 , wherein the semiconductor comprises an n-type doped group IV semiconductor and comprises a source or drain of a transistor.

64. The electrical junction of claim 54 , wherein the semiconductor comprises an n-type doped group IV semiconductor and comprises a source or drain of a transistor, and the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .

65. An electrical junction comprising an interface layer disposed between a contact metal and a group IV semiconductor, the interface layer comprising a metal oxide and configured to reduce a height of a Schottky barrier between the contact metal and the semiconductor from that which would exist at a contact junction between the contact metal and the semiconductor without the interface layer disposed therebetween, and wherein the electrical junction has a specific contact resistance of less than or equal to approximately 1000 Ω-μm 2 , wherein the contact metal is a metal or a stack of metals deposited on the interface layer.

66. The electrical junction of claim 65 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm 2 .

67. The electrical junction of claim 65 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

68. An electrical junction comprising an interface layer disposed between a contact metal and a semiconductor, the interface layer being a metal oxide and sufficiently thick to depin a Fermi level of the semiconductor, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-μm 2 , wherein the contact metal is a metal or a stack of metals deposited on the interface layer.

69. The electrical junction of claim 68 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm 2 .

70. The electrical junction of claim 68 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

71. An electrical junction, comprising a conductor; a semiconductor selected from a list consisting of Si, Ge, C (a crystal structure of which is selected from a list comprising a diamond lattice, a fulleride or a polymer), an alloy of Ge and Si, an alloy of Ge and C, an alloy of Si and C, and an alloy of Si, Ge, and C; and an interface layer disposed therebetween, the interface layer comprising a metal oxide and being sufficiently thick to approximately equal a penetration depth of metal induced gap states (MIGS) in the semiconductor which would be present the interface layer were absent, yet sufficiently thin to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-μm 2 , wherein the conductor is a metal or a stack of metals deposited on the interface layer.

72. The electrical junction of claim 71 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm 2 .

73. The electrical junction of claim 71 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

74. An electrical junction, comprising a semiconductor and a conductor separated from the semiconductor by an interface layer comprising a metal oxide and having a thickness sufficient to depin a Fermi level of the conductor in a vicinity of the junction yet thin enough to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-μm 2 , wherein the conductor is a metal or a stack of metals deposited on the interface layer.

75. The electrical junction of claim 74 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm 2 .

76. The electrical junction of claim 75 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

77. An electrical junction, comprising an n-type doped Si semiconductor and a conductor separated from the semiconductor by an interface layer comprising a metal oxide and having a thickness sufficient to depin a Fermi level of the conductor in a vicinity of the junction yet thin enough to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-μm 2 .

78. The electrical junction of claim 77 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm 2 .

79. The electrical junction of claim 77 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

80. The electrical junction of claim 77 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .

81. An electrical junction, comprising a p-type doped semiconductor and a conductor separated from the semiconductor by an interface layer comprising a metal oxide and having a thickness sufficient to depin a Fermi level of the conductor in a vicinity of the junction yet thin enough to provide the junction with a specific contact resistance of less than or equal to approximately 1000 Ω-μm 2 .

82. The electrical junction of claim 81 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 100 Ω-μm 2 .

83. The electrical junction of claim 81 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 10 Ω-μm 2 .

84. The electrical junction of claim 81 , wherein the electrical junction has a specific contact resistance of less than or equal to approximately 1 Ω-μm 2 .