IP Library Granted Patent US 8,766,428
Granted Patent B2
US 8,766,428 · App. 12/629,879 · Granted Jul 1, 2014

Integrated circuit packaging system with flip chip and method of manufacture thereof

Inventors: Zigmund Ramirez Camacho (Singapore, SG); Henry Descalzo Bathan (Singapore, SG); Jairus Legaspi Pisigan (Singapore, SG)
Assignee: Stats Chippac Ltd.
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Quick Facts
Patent No.
US 8,766,428
App. No.
12/629,879
Granted
Jul 1, 2014
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: forming external interconnects having bases of a first thickness and tips of a second thickness extending inwardly directly toward each other; connecting a first circuit device between the tips; attaching a second circuit device to the first circuit device with a combined thickness of the first circuit device and the second circuit device less than the first thickness; and forming an encapsulation of the first thickness between the bases and over the tips.

Claims (72)

1. A method of manufacture of an integrated circuit packaging system comprising:

forming external interconnects having bases of a first thickness and tips of a second thickness extending inwardly directly toward each other, each of the tips include a bottom surface;

connecting a first circuit device between the tips, the first circuit device having a first circuit device active side with a mounting pad therein and having a first circuit device non-active side, the first circuit device non-active side is coplanar with the bottom surface and another of the bottom surface of the tips;

attaching a second circuit device over the first circuit device, the second circuit device having a second circuit device active side with a contact pad therein and a device interconnect, the device interconnect directly connected to the contact pad and the mounting pad with a combined thickness of the first circuit device and the second circuit device less than the first thickness; and

forming an encapsulation of the first thickness between the bases and over the tips.

2. The method as claimed in claim 1 further comprising:

forming a paddle adjacent to and between the bases of the external interconnects;

mounting the second circuit device over the paddle; and

wherein forming the encapsulation includes:

forming the encapsulation with the paddle exposed.

3. The method as claimed in claim 1 further comprising:

forming a paddle adjacent to and between the tips of the external interconnects;

mounting the first circuit device over the paddle; and

wherein forming the encapsulation includes:

forming the encapsulation with the paddle exposed.

4. The method as claimed in claim 1 further comprising forming the first circuit device having a horizontal dimension greater than a horizontal dimension of the second circuit device.

5. The method as claimed in claim 1 wherein:

forming the external interconnects includes forming the external interconnects having an external interconnect first side, an external interconnect second side, and an external interconnect vertical side; and

forming the encapsulation includes forming the encapsulation with the external interconnect first side, the external interconnect second side, and the external interconnect vertical side exposed.

6. A method of manufacture of an integrated circuit packaging system comprising:

forming external interconnects each having an external interconnect first side, an external interconnect second side, an external interconnect vertical side, bases of a first thickness, and tips of a second thickness extending inwardly directly toward each other;

connecting a first circuit device between the tips with the first circuit device having a first circuit device active side with a mounting pad therein and having a first circuit device non-active side, the first circuit device non-active side is coplanar with the external interconnect first side of each of the tips;

attaching a second circuit device over the first circuit device, the second circuit device having a second circuit device active side with a contact pad therein and a device interconnect, the device interconnect directly connected to the contact pad and the mounting pad with a combined thickness of the first circuit device and the second circuit device less than the first thickness; and

forming an encapsulation of the first thickness between the bases and over the tips.

7. The method as claimed in claim 6 further comprising:

forming a paddle adjacent to and between the bases of the external interconnects;

mounting the second circuit device over the paddle; and

wherein forming the encapsulation includes:

forming the encapsulation first side coplanar with and exposing the paddle; and

forming the encapsulation second side coplanar with and exposing the first circuit device non-active side.

8. The method as claimed in claim 6 further comprising:

forming a paddle adjacent to and between the tips of the external interconnects;

mounting the first circuit device over the paddle; and

wherein forming the encapsulation includes:

forming the encapsulation first side coplanar with and exposing the paddle; and

forming the encapsulation second side coplanar with and exposing the second circuit device.

9. The method as claimed in claim 6 wherein forming the encapsulation includes:

forming the encapsulation first side coplanar with the external interconnect first side; and

forming the encapsulation second side coplanar with the external interconnect second side.

10. The method as claimed in claim 6 wherein attaching the second circuit device includes connecting a flip chip.

11. An integrated circuit packaging system comprising:

external interconnects having bases of a first thickness and tips of a second thickness extending inwardly directly toward each other, each of the tips include a bottom surface;

a first circuit device connected between the tips, the first circuit device having a first circuit device active side with a mounting pad therein and having a first circuit device non-active side, the first circuit device non-active side is coplanar with the bottom surface and another of the bottom surface of the tips;

a device interconnect directly connected to the mounting pad;

a second circuit device over the first circuit device, the second circuit device having a second circuit device active side with a contact pad therein and a device interconnect, the device interconnect directly connected to the contact pad and the mounting pad with a combined thickness of the first circuit device and the second circuit device less than the first thickness; and

an encapsulation of the first thickness between the bases and over the tips.

12. The system as claimed in claim 11 further comprising:

a paddle adjacent to and between the bases of the external interconnects and exposed from the encapsulation; and

wherein the second circuit device is mounted over the paddle.

13. The system as claimed in claim 11 further comprising:

a paddle adjacent to and between the tips of the external interconnects and exposed from the encapsulation; and

wherein the first circuit device is mounted over the paddle.

14. The system as claimed in claim 11 further comprising the first circuit device having a horizontal dimension greater than a horizontal dimension of the second circuit device.

15. The system as claimed in claim 11 wherein the external interconnects includes an external interconnect first side, an external interconnect second side, and an external interconnect vertical side with the external interconnect first side, the external interconnect second side, and the external interconnect vertical side exposed from the encapsulation.

16. The system as claimed in claim 11 wherein:

the external interconnects includes an external interconnect first side, an external interconnect second side, and an external interconnect vertical side;

the second circuit device includes a second circuit device active side and a second circuit device non-active side; and

the encapsulation includes an encapsulation first side and an encapsulation second side.

17. The system as claimed in claim 16 further comprising:

a paddle adjacent to and between the bases of the external interconnects and exposed from the encapsulation first side; and

wherein:

the second circuit device is mounted over the paddle;

the encapsulation having the encapsulation second side is coplanar with and exposing the first circuit device non-active side.

18. The system as claimed in claim 16 further comprising:

a paddle adjacent to and between the tips of the external interconnects and exposed from the encapsulation first side; and

wherein:

the first circuit device is mounted over the paddle; and

the second circuit device is exposed from and coplanar with the encapsulation second side.

19. The system as claimed in claim 16 wherein the encapsulation includes:

the encapsulation first side coplanar with the external interconnect first side; and

the encapsulation second side coplanar with the external interconnect second side.

20. The system as claimed in claim 16 wherein the second circuit device includes a flip chip.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE." TO "STATS CHIPPAC PTE. LTD." PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0208. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0387 →
RELEASE OF SECURITY INTEREST Recorded Jun 4, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052844/0491 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0208 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2009
From: CAMACHO, ZIGMUND RAMIREZ; BATHAN, HENRY DESCALZO; PISIGAN, JAIRUS LEGASPI
To: STATS CHIPPAC LTD.
Reel/Frame 023637/0503 →
Continuity (1)
Related Publication 20110127661A1 · Jun 2, 2011