Granted Patent B2

US 8,767,476 · App. 13/093,411 · Granted Jul 1, 2014

Inventors: Violante Moschiano (Bacoli, IT); Daniel Elmhurst (Folsom, CA); Paul Ruby (Folsom, CA)

Assignee: Micron Technology, Inc.

Abstract

Claims (68)

1. A method of operating a memory, comprising:

determining a quick charge loss compensation for at least one block of the memory; and

adjusting a wordline voltage of the memory according to the quick charge loss compensation, wherein quick charge loss compensation is determined using mean threshold voltages of a tracking block at different times.

2. The method of claim 1 , wherein determining a quick charge loss compensation further comprises:

wear leveling program blocks in the memory;

programming a tracking block in the memory with the at least one block of the memory in accordance with a specific pattern;

determining a mean threshold voltage for the tracking block;

erasing the tracking block when its block of the memory is erased; and

re-programming the tracking block in accordance with the specific pattern when its block of the memory is programmed.

3. The method of claim 2 , wherein adjusting a wordline voltage comprises adjusting the wordline voltage level equal to a difference between the mean threshold voltage and a mean threshold voltage for the tracking block after the re-programming.

4. The method of claim 2 , wherein the tracking block is programmed as a single redundant memory block for one block of the memory.

5. The method of claim 2 , wherein the tracking block is a plurality of mini-arrays, each block of the memory having a separate mini-array or a portion thereof associated therewith.

6. The method of claim 1 , wherein determining a quick charge loss compensation comprises:

programming at least a portion of a mini-array in the memory for each of the blocks of the memory in accordance with a specific pattern;

determining a mean threshold voltage for the at least a portion of each mini-array;

completing a mini-array margin search on the at least a portion of the mini-array block when its associated main array block is read;

determining a difference between a mean threshold voltage of the at least a portion of the mini-array upon reading a program block associated with the at least a portion of the mini-array and the mean threshold voltage for the at least a portion of the mini-array;

re-programming the at least a portion of the mini-array in accordance with the specific pattern when its associated block is programmed; and

adjusting a wordline voltage level by the difference.

7. The method of claim 6 , wherein programming of the at least a portion of a mini-array is contemporaneous to programming of its associated program block.

8. A method of operating a memory, comprising:

wear leveling program blocks in the memory;

programming a program block of the memory and a redundant block of the memory in accordance with a specific pattern;

determining a mean uncycled threshold voltage for the redundant block;

erasing the redundant block when its program block is erased;

re-programming the redundant block in accordance with the specific pattern when its program block is programmed;

determining a current post-cycled mean threshold voltage for the redundant block; and

adjusting a wordline voltage level.

9. The method of claim 8 , wherein adjusting further comprises raising the wordline voltage level by an amount equal to a difference between the uncycled mean threshold voltage and the current post-cycled mean threshold voltage for the redundant block.

10. The method of claim 8 , wherein adjusting a wordline voltage level further comprises adjusting based on the mean uncycled threshold voltage and the current post-cycled mean threshold voltage.

11. A method of operating a memory, comprising:

for each program block in the memory, programming the program block and at least a portion of a mini-array in accordance with a specific pattern;

determining a mean uncycled threshold voltage for each at least a portion of a mini-array;

completing a mini-array margin search on the at least a portion of a mini-array block when its respective program block is read to determine a difference between its current post-cycled threshold voltage mean and the mean uncycled threshold voltage for the at least a portion of the mini-array;

re-programming the at least a portion of the mini-array in accordance with the specific pattern when its respsective block is programmed; and

adjusting a wordline voltage level by an amount equal to the difference.

12. The method of claim 11 , wherein for each program block, programming the at least a portion of a mini-array comprises allocating a page or a portion of a page of a mini-array to each program block.

13. A memory device, comprising:

an array of non-volatile memory cells, having a plurality of program blocks; and

a tracking block associated with one of the program blocks, the tracking block to store a mean threshold voltage to allow determination of quick charge loss compensation for the associated program block.

14. The memory device of claim 13 , and further comprising:

logic circuitry on the memory to store an original mean threshold voltage of the tracking block and to compare the original mean threshold voltage to the mean threshold voltage to determine the quick charge loss compensation.

15. A memory device, comprising:

an array of non-volatile memory cells, having a plurality of main program array blocks, arranged in rows and columns;

control circuitry to read, write and erase the memory cells;

address circuitry to latch address signals provided on address input connections; and

a plurality of mini-arrays, a mini-array or a portion thereof associated with one of the main program array blocks, each mini-array or portion thereof to store current post-cycled mean threshold voltage of its associated main program array block to allow determination of charge loss compensation for its main program array block.

16. The memory device of claim 15 , wherein each mini-array comprises a plurality of blocks.

17. The memory device of claim 15 , and further comprising:

logic circuitry on the memory to store an uncycled mean threshold voltage of each mini-array or portion thereof and to compare the uncycled mean threshold voltage to the current post-cycled mean threshold voltage to determine the charge loss compensation for its main program array block.

18. A memory device, comprising:

an array of non-volatile memory cells, having a plurality of program blocks and a tracking block, the memory cells accessed by bitlines and word lines; and

circuitry for control and/or access of the array of non-volatile memory cells, the control circuitry adapted to perform a method comprising:

wear leveling program blocks in the memory;

for each program block of the memory, programming the program block and a redundant block of the memory in accordance with a specific pattern;

determining a mean uncycled threshold voltage for the redundant block;

erasing the redundant block when its program block is erased;

re-programming the redundant block in accordance with the specific pattern when its program block is programmed;

determining a difference between the mean uncycled threshold voltage and a current mean threshold voltage for the redundant block; and

adjusting a wordline voltage level by the difference.

19. A memory device, comprising:

an array of non-volatile memory cells, having a plurality of program blocks and a tracking block comprising at least a portion of a mini-array, the memory cells accessed by bitlines and word lines; and

circuitry for control and/or access of the array of non-volatile memory cells, the control circuitry adapted to perform a method comprising:

for each program block in the memory, programming the program block and at least a portion of a mini-array in accordance with a specific pattern;

determining a mean uncycled threshold voltage for each at least a portion of a mini-array;

completing a mini-array margin search on a mini-array block or portion thereof when its program block is read to determine a difference between a current mean threshold voltage of the mini-array block or portion thereof and the uncycled mean for the mini-array or portion thereof;

re-programming the mini-array with the specific pattern when its program block is programmed; and

adjusting a wordline voltage by an amount equal to the difference.

Assignments (8)

Continuity (2)