Dynamic fault detection and repair in a data communications mechanism

1. A communications mechanism for communicating between digital data devices, comprising:

a first plurality of parallel lines supporting a parallel communications link having N logical lanes for communicating data in a first direction from a first digital data device to a second digital data device, said first plurality of parallel lines comprising at least (N+1) lines;

a calibration mechanism for periodically recalibrating lines of said first plurality of parallel lines;

a switching mechanism coupled to said calibration mechanism for selectively enabling each line of said first plurality of parallel lines to carry functional data, said switching mechanism disabling a line of said first plurality of parallel lines for calibration by said calibration mechanism while N lines of said first plurality of parallel lines not being calibrated are enabled for carrying functional data;

a line fault detection mechanism for detecting a line fault in any of said first plurality of parallel lines;

a line replacement mechanism coupled to said line fault detection mechanism and said switching mechanism, said line replacement mechanism responding to a detected line fault in a faulty line of said first plurality of parallel lines by causing said switching mechanism to disable the faulty line and enable previously calibrated lines of said first plurality of parallel lines other than the faulty line to carry functional data, said previously calibrated lines of said first plurality of parallel lines being calibrated prior to detection of the line fault

a second plurality of parallel lines supporting a parallel link having P logical lanes for communicating data in a second direction from said second digital data device to said first digital data device, said second plurality of parallel lines comprising at least (P+1) lines;

wherein said calibration mechanism is further for periodically recalibrating said second plurality of parallel lines;

wherein said switching mechanism is further for selectively enabling each line of said second plurality of parallel lines to carry functional data, said switching mechanism disabling a line of said second plurality of parallel lines for calibration by said calibration mechanism while P lines of said second plurality of parallel lines not being calibrated are enabled for carrying functional data;

wherein said line fault detection mechanism is further for detecting a line fault in and of said second plurality of parallel lines;

wherein said line replacement mechanism further responds to a detected line fault in a faulty line of said second plurality of parallel lines by causing said switching mechanism to disable the faulty line of said second plurality of parallel lines and enable previously calibrated lines of said second plurality of parallel lines other than the faulty line to carry functional data, said previously calibrated lines of said second plurality of parallel lines being calibrated prior to detection of the line fault.

2. The communications mechanism of claim 1 , wherein said first plurality of parallel lines comprises at least (N+2) lines, including at least one spare line which is not used for carrying functional data in the absence of a line fault detected by said line fault detection mechanism.

3. The communications mechanism of claim 2 ,

wherein, in the absence of a line fault detected by said line fault detection mechanism, said spare line is powered off;

wherein responsive to a line fault detected by said line fault detection mechanism, said line replacement mechanism causes said spare line to be powered on and calibrated by said calibration mechanism; and

wherein said line replacement mechanism causes said switching mechanism to disable the faulty line and enable N previously calibrated lines of said first plurality of parallel lines other than the faulty line to carry functional data without waiting for said spare line to be powered on and calibrated.

4. The communications mechanism of claim 1 ,

wherein a line of said first plurality of parallel lines disabled by said switching mechanism for calibration by said calibration mechanism is time multiplexed to further transmit control signals in said first direction from said first digital device to said second digital device; and

wherein a line of said second plurality of parallel lines disabled by said switching mechanism for calibration by said calibration mechanism is time multiplexed to further transmit control signals in said second direction from said second digital device to said first digital device.

5. The communications mechanism of claim 1 ,

wherein said line fault detection mechanism detects a fault in said faulty line by detecting at least one of: (a) an excessive occurrence of errors in functional data transmitted on the faulty line, and (b) a calibration anomaly with respect to the faulty line.

6. A communications mechanism for communicating between digital data devices, comprising:

a first plurality of parallel lines supporting a parallel communications link having N logical lanes for communicating data in a first direction from a first digital data device to a second digital data device, said first plurality of parallel lines comprising at least (N+1) lines;

a switching mechanism for selectively enabling each line of said first plurality of parallel lines to carry functional data, said switching mechanism disabling a line of said first plurality of parallel lines while N lines of said first plurality of parallel lines are enabled for carrying functional data;

a logical lane error detection mechanism for detecting errors in the output of said switching mechanism, said logical lane error detection mechanism identifying, for each of a plurality of detected errors, a respective logical lane corresponding to the respective error;

a mapping mechanism coupled to said logical lane error detection mechanism for determining, for each error detected by said logical lane error detection mechanism, a respective line of said first plurality of parallel lines carrying functional data corresponding to the respective logical lane corresponding to the respective error; and

an error accumulation detection mechanism coupled to said mapping mechanism for detecting an excessive occurrence of errors in a single line of said first plurality of parallel lines

a second plurality of parallel lines supporting a parallel link having P logical lanes for communicating data in a second direction from said second digital data device to said first digital data device, said second plurality of parallel lines comprising at least (P+1) lines;

wherein said calibration mechanism is further for periodically recalibrating said second plurality of parallel lines;

wherein said switching mechanism is further for selectively enabling each line of said second plurality of parallel lines to carry functional data, said switching mechanism disabling a line of said second plurality of parallel lines for calibration by said calibration mechanism while P lines of said second plurality of parallel lines not being calibrated are enabled for carrying functional data;

wherein said line fault detection mechanism is further for detecting a line fault in and of said second plurality of parallel lines;

wherein said line replacement mechanism further responds to a detected line fault in a faulty line of said second plurality of parallel lines by causing said switching mechanism to disable the faulty line of said second plurality of parallel lines and enable previously calibrated lines of said second plurality of parallel lines other than the faulty line to carry functional data, said previously calibrated lines of said second plurality of parallel lines being calibrated prior to detection of the line fault.

7. The communications mechanism of claim 6 , further comprising:

a calibration mechanism for periodically recalibrating lines of said first plurality of parallel lines;

wherein said switching mechanism disables a line of said first plurality of parallel lines for calibration by said calibration mechanism while N lines of said first plurality of parallel lines not being calibrated are enabled for carrying functional data.

8. The communications mechanism of claim 6 , further comprising:

a line repair mechanism coupled to said error accumulation detection mechanism and said switching mechanism, said line repair mechanism responding to an excessive occurrence of errors in a first line of said first plurality of parallel lines detected by said error accumulation detection mechanism by assigning functional data otherwise transmitted by the first line to at least one other line of said first plurality of parallel lines.

9. The communications mechanism of claim 8 , wherein said first plurality of parallel lines includes a spare line which is not used for carrying functional data in the absence of an excessive occurrence of errors detected by said error accumulation detection mechanism, said line repair mechanism responding to an excessive occurrence of errors in the first line detected by said error accumulation detection mechanism by activating said spare line.

10. The communications mechanism of claim 8 ,

wherein said communications mechanism further comprises a calibration mechanism for periodically recalibrating lines of said first plurality of parallel lines;

wherein responsive to an excessive occurrence of errors in the first line detected by said error accumulation detection mechanism, said line repair mechanism causes a logical lane width of said communications link to be reduced to (N 1) logical lanes for communicating data in said first direction from said first digital data device to said second digital data device; and

wherein said switching mechanism thereafter disables a line of said first plurality of parallel lines other than said faulty line for calibration by a calibration mechanism while (N 1) lines of said first plurality of parallel lines not being calibrated other than said faulty line are enabled for carrying functional data.

11. The communications mechanism of claim 6 , wherein said logical lane error detection mechanism detects errors by computing a cyclic redundancy check (CRC) of functional data output by said switching mechanism.

12. The communications mechanism of claim 6 , wherein said error accumulation detection mechanism comprises a counter and a line identifier register, said counter representing a number of consecutive detected errors in data output by said switching mechanism corresponding to a single line of said plurality of parallel lines, and said line identifier register identifying the single line of said plurality of parallel lines to which the consecutive errors correspond.