Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning
The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
1. A memory line layout method comprising:
forming a plurality of memory lines extending from one or more memory array blocks wherein the memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines; and
forming a plurality of zia contact areas having a dimension larger than the nominal minimum feature size capability of the lithography tool,
wherein the memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas.
2. The memory line layout method of claim 1 , wherein the memory lines are formed via a sidewall defined process.
3. The memory line layout method of claim 1 , wherein the memory lines extend in interleaved pairs from opposite sides of the memory array blocks.
4. The memory line layout method of claim 3 , wherein a cut shape having a dimension larger than the nominal minimum feature size capability of the lithography tool is positioned on each of a subset of pairs of memory lines.
5. The memory line layout method of claim 4 , wherein the cut shape includes a dimension that is four times the half pitch of the memory lines.
6. The memory line layout method of claim 1 , wherein the pattern of the memory lines is a staggered pattern.
7. The memory line layout method of claim 1 , wherein the pattern of the memory lines is a stepped pattern.
8. The memory line layout method of claim 1 , wherein the pattern of the memory lines is a combination of a staggered and stepped pattern.
9. The memory line layout method of claim 1 , wherein the zia contact areas include a dimension that is four times the half pitch of the memory lines.
10. A three-dimensional memory comprising:
a plurality of memory layers coupled together by a plurality of zias, each zia including a zia contact area on at least one memory layer,
wherein each memory layer includes one or more memory array blocks coupled to memory lines,
wherein the memory lines extend from the memory array blocks,
wherein the memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines,
wherein the zia contact areas have a dimension larger than the nominal minimum feature size capability of the lithography tool, and
wherein the memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas.
11. The three-dimensional memory of claim 10 , wherein the memory lines are formed via a sidewall defined process.
12. The three-dimensional memory of claim 10 , wherein the memory lines extend in interleaved pairs from opposite sides of the memory array blocks.
13. The three-dimensional memory of claim 12 , wherein a cut shape having a dimension larger than the nominal minimum feature size capability of the lithography tool is positioned on each of a subset of pairs of memory lines.
14. The three-dimensional memory of claim 13 , wherein the cut shape includes a dimension that is four times the half pitch of the memory lines.
15. The three-dimensional memory of claim 10 , wherein the pattern of the memory lines is a staggered pattern.
16. The three-dimensional memory of claim 10 , wherein the pattern of the memory lines is a stepped pattern.
17. The three-dimensional memory of claim 10 , wherein the pattern of the memory lines is a combination of a staggered and stepped pattern.
18. The three-dimensional memory of claim 10 , wherein the zia contact areas include a dimension that is four times the half pitch of the memory lines.
19. A memory layer for a three-dimensional memory, the memory layer comprising:
one or more memory array blocks;
a plurality of memory lines coupled to the memory array blocks; and
a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory,
wherein the memory lines extend from the memory array blocks,
wherein the memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines,
wherein the zia contact areas have a dimension larger than the nominal minimum feature size capability of the lithography tool, and
wherein the memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas.
20. The memory layer of claim 19 , wherein the memory lines are formed via a sidewall defined process.
21. The memory layer of claim 19 , wherein the memory lines extend in interleaved pairs from opposite sides of the memory array blocks.
22. The memory layer of claim 21 , wherein a cut shape having a dimension larger than the nominal minimum feature size capability of the lithography tool is positioned on each of a subset of pairs of memory lines.
23. The memory layer of claim 22 , wherein the cut shape includes a dimension that is four times the half pitch of the memory lines.
24. The memory layer of claim 19 , wherein the pattern of the memory lines is a staggered pattern.
25. The memory layer of claim 19 , wherein the pattern of the memory lines is a stepped pattern.
26. The memory layer of claim 19 , wherein the pattern of the memory lines is a combination of a staggered and stepped pattern.
27. The memory layer of claim 19 , wherein the zia contact areas include a dimension that is four times the half pitch of the memory lines.
28. A memory layer for a three-dimensional memory, the memory layer comprising:
a plurality of memory array blocks;
a plurality of memory lines coupled to the memory array blocks; and
a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory,
wherein the memory lines extend from the memory array blocks and are formed using a sidewall defined process,
wherein the memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines,
wherein the zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines, and
wherein the memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas.