Tucked active region without dummy poly for performance boost and variation reduction
View Patent ↗In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.
1. A method of forming a semiconductor device comprising:
providing a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region;
forming a plurality of replacement gate structures on the active region of the semiconductor substrate, wherein at least one interface replacement gate structure of the plurality of replacement gate structures is formed having a first bottommost surface portion in direct physical contact with a topmost surface of the semiconductor substrate in the active region and a second bottommost surface portion in directly physical contact with a topmost surface of the at least one trench isolation region, and at least one device replacement gate structure of the plurality of replacement gate structures is formed on a portion of the active region that is separated from the at least one trench isolation region;
forming embedded semiconductor regions in the active region of the semiconductor substrate between adjacent replacement gate structures of the plurality of replacement gate structures, wherein the embedded semiconductor region formed between the at least one interface replacement gate structure and the neighboring device replacement gate structure has an outermost edge that is laterally separated from the at least one trench isolation region by another portion of the active region of the semiconductor substrate underneath the first bottommost surface portion of the at least one interface replacement gate structure;
replacing the at least one device replacement gate structure with a functional gate structure; and
removing at least a portion of the at least one interface replacement gate structure.
2. The method of claim 1 , wherein each replacement gate structure in the plurality of gate structures includes a gate stack of a sacrificial gate conductor structure and a gate dielectric, and a spacer adjacent to the gate stack.
3. The method of claim 2 , wherein the removing of at least the portion of the interface replacement gate structure comprises removing the sacrificial gate conductor structure and the spacer, wherein the gate dielectric of the interface replacement gate structure remains.
4. The method of claim 2 , wherein the removing of at least the portion of the interface replacement gate structure comprises removing the sacrificial gate conductor structure and the gate dielectric, wherein the spacer remains.
5. The method of claim 2 , wherein the removing of at least the portion of the interface replacement gate structure comprises entirely removing the interface replacement gate structure.
6. The method of claim 1 , wherein the forming of the embedded semiconductor regions in the active region of the semiconductor substrate between adjacent replacement gate structures of the plurality of replacement gate structures comprises etching an exposed portion of the active region between adjacent replacement gate structures to form a well trench; and epitaxially forming a semiconductor material having a different composition than the semiconductor substrate within the well trench.
7. The method of claim 6 , wherein a remaining portion of the active region of the semiconductor substrate is present between the trench and the at least one isolation region.
8. The method of claim 6 , wherein the removing of at least the portion of the interface replacement gate structure comprises removing a sacrificial gate conductor structure, wherein a spacer and the gate dielectric of the interface replacement gate structure remain.
9. The method of claim 1 , wherein the semiconductor substrate is comprised of silicon and the embedded semiconductor regions are comprised of silicon germanium.
10. The method of claim 1 , further comprising forming source regions and drain regions on opposing sides of the portion of the semiconductor substrate that the device replacement gate structure is formed on.
11. The method of claim 10 , wherein the forming of the source regions and the drain regions comprises ion implantation.
12. The method of claim 1 , wherein said forming said embedded semiconductor regions comprises an in-situ doped epitaxial growth process, wherein said embedded semiconductor regions on one side of each device replacement gate structure comprise a source region and said embedded semiconductor regions on another side of each device replacement gate structure comprise a drain region.