Wafer dicing using femtosecond-based laser and plasma etch
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.
1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a mask above the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits;
patterning the mask and a portion of the semiconductor wafer with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits, wherein each of the trenches has a width; and
plasma etching the semiconductor wafer through the trenches to form corresponding trench extensions and to singulate the integrated circuits, wherein each of the corresponding trench extensions has the width.
2. The method of claim 1 , wherein plasma etching the semiconductor wafer comprises using a high density plasma etching process.
3. The method of claim 1 , wherein forming the mask comprises forming a layer selected from the group consisting of a photo-resist layer and an I-line patterning layer.
4. The method of claim 1 , wherein each of the plurality of integrated circuits is separated by streets having a width of approximately 10 microns or smaller as measured at a device layer/substrate interface.
5. The method of claim 1 , wherein the plurality of integrated circuits has a non-restricted layout.
6. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:
forming a polymer layer above a silicon substrate, the polymer layer covering and protecting integrated circuits disposed on the silicon substrate, the integrated circuits comprising a layer of silicon dioxide disposed above a layer of low K material and a layer of copper;
patterning the polymer layer, the layer of silicon dioxide, the layer of low K material, the layer of copper and a portion of the silicon substrate with a laser scribing process to form trenches partially into but not through the silicon substrate between the integrated circuits, wherein each of the trenches has a width; and
plasma etching the silicon substrate through the trenches to form corresponding trench extensions and to singulate the integrated circuits, wherein each of the corresponding trench extensions has the width.
7. The method of claim 6 , wherein patterning the layer of silicon dioxide, the layer of low K material, the layer of copper and the portion so the silicon substrate with the laser scribing process comprises ablating the layer of silicon dioxide prior to ablating the layer of low K material and the layer of copper.
8. The method of claim 6 , wherein plasma etching the silicon substrate comprises using a high density through-silicon plasma etching process.
9. The method of claim 6 , wherein each of the plurality of integrated circuits is separated from one another by streets having a width of approximately 10 microns or smaller.
10. The method of claim 6 , wherein the plurality of integrated circuits has a non-restricted layout.