3-D integration using multi stage vias
View Patent ↗A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV is can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias.
1. A TSV extending from a top surface of a semiconductor substrate to a bottom surface of said substrate, said TSV comprising:
a single first via section extending from said top surface and into said substrate, wherein the first via section has a first cross section;
a second via section extending from said bottom surface to said first via section, wherein the second via section has a second cross section, and wherein the second cross section is greater than or equal to the first cross section; and
a conductive path formed of a continuous single material extending within said first and second via sections from said top surface to said bottom surface, wherein the second via section further comprises an annular coating of said single material, and a dielectric material is disposed on an interior surface of said annular coating and in the center of the second via section.
2. The structure of claim 1 , further comprising a dielectric liner separating said conductive path from said substrate.
3. The structure of claim 1 , wherein said first via section is lined with thermal oxide.
4. The structure of claim 1 further comprising at least two first via sections.
5. The structure of claim 4 wherein one of said first via sections has different dimensions from another of said first via sections.
6. The structure of claim 5 wherein a plurality of dielectric layers is disposed on said top surface, wherein said one of said first via sections extends through a greater depth of said plurality of dielectric layers than said another of said first via sections.
7. The structure of claim 1 wherein said conductive path is asymmetric about the TSV axis.
8. The structure of claim 1 wherein said conductive path comprises W or Cu or an alloy of W or Cu.
9. The structure of claim 1 wherein at least one semiconductor device is formed within said top surface.
10. The structure of claim 1 wherein said conductive path comprises polysilicon.
11. The structure of claim 1 wherein a second top via section extends from a second contact disposed above said top surface and to said bottom via section.