Low resistivity gate conductor
Embodiments of the invention provide an approach for bottom-up growth of a low resistivity gate conductor. Specifically, a low resistivity metal (e.g., aluminum or cobalt) is selectively grown directly over metal layers in a set of gate trenches using a chemical vapor deposition or atomic layer deposition process to form the gate conductor.
1. A method for forming a device, the method comprising:
forming a set of trenches in a dielectric material;
forming a low-resistivity gate conductor atop each of a set of metal layers in each of the set of trenches, the low-resistivity gate conductor directly abutting a set of sidewall spacers of the set of trenches; and
forming a capping layer over the low-resistivity gate conductor.
2. The method according to claim 1 , the forming the set of trenches in the dielectric material comprising performing an etch.
3. The method according to claim 1 , the set of metal layers comprising at least one of: titanium nitride and titanium carbide.
4. The method according to claim 1 , the low-resistivity gate conductor comprising at least one of: aluminum, cobalt, and nitride.
5. The method according to claim 1 , the forming the low-resistivity gate conductor comprising one of: atomic layer deposition, and chemical vapor deposition.
6. The method according to claim 1 , the capping layer comprising silicon nitride.
7. The method according to claim 1 , wherein the dielectric material comprises a high-k dielectric.
8. A method for forming a semiconductor gate stack, the method comprising:
forming a set of trenches in a dielectric material;
forming a low-resistivity gate conductor atop each of a set of metal layers in each of the set of trenches, the low-resistivity gate conductor directly abutting a set of sidewall spacers of the set of trenches; and
forming a capping layer over the low-resistivity conductive metal.
9. The method according to claim 8 , the forming the set of trenches in the dielectric material comprising performing an etch.
10. The method according to claim 8 , the set of metal layers comprising at least one of: titanium nitride, and titanium carbide.
11. The method according to claim 8 , the low-resistivity conductive metal comprising at least one of: aluminum, cobalt, and nitride.
12. The method according to claim 8 , the forming the low-resistivity conductive metal comprising one of: atomic layer deposition, and chemical vapor deposition.
13. The method according to claim 8 , the capping layer comprising silicon nitride.
14. The method according to claim 8 , wherein the dielectric material comprises a high-k dielectric.
15. A semiconductor device, comprising:
a low-resistivity conductive metal formed directly atop each of a set of metal layers in each of a plurality of trenches in a dielectric material, the low-resistivity gate conductor directly abutting a set of sidewall spacers of the set of trenches; and
a capping layer formed over the low-resistivity conductive metal.
16. The device according to claim 15 , wherein the plurality of trenches in the dielectric material are formed by an etch.
17. The device according to claim 15 , the set of metal layers comprising at least one of: titanium nitride, and titanium carbide.
18. The device according to claim 15 , the low-resistivity conductive metal comprising at least one of: aluminum, cobalt, and nitride.
19. The device according to claim 15 , the low-resistivity conductive metal formed by one of: atomic layer deposition, and chemical vapor deposition.
20. The device according to claim 15 , the capping layer comprising silicon nitride, and the dielectric material comprising a high-k dielectric.