IP Library Granted Patent US 8,900,975
Granted Patent B2
US 8,900,975 · App. 13/733,404 · Granted Dec 2, 2014

Nanopore sensor device

Inventors: Josephine B. Chang (Mahopac, NY); Michael A. Guillorn (Yorktown Heights, NY); Eric A. Joseph (White Plains, NY); Satyavolu S. Papa Rao (Poughkeepsie, NY)
Assignee: International Business Machines Corporation
H01L29/66007H01L29/66G01N33/54373
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Quick Facts
Patent No.
US 8,900,975
App. No.
13/733,404
Granted
Dec 2, 2014
Kind
B2
Abstract

A pair of electrode plates can be provided by directional deposition and patterning of a conductive material on sidewalls of a template structure on a first dielectric layer. An electrode line straddling the center portion is formed. A dielectric spacer and a conformal conductive layer are subsequently formed. Peripheral electrodes laterally spaced from the electrode line are formed by pattering the conformal conductive layer. After deposition of a second dielectric material layer that encapsulates the template structure, the template structure is removed to provide a cavity that passes through the pair of electrode plates, the electrode line, and the peripheral electrodes. A nanoscale sensor thus formed can electrically characterize a nanoscale string by passing the nanoscale string through the cavity while electrical measurements are performed employing the various electrodes.

Claims (56)

1. A method of forming a sensor structure, said method comprising:

forming a template structure on a first dielectric material layer,

forming an electrode line straddling said template structure;

forming a dielectric spacer around said electrode line;

forming peripheral electrodes laterally spaced from said electrode line by said dielectric spacer;

forming a second dielectric material layer over said template structure; and

removing said template structure selective to said first and second dielectric material layers to form a cavity, wherein a sensor structure comprising said cavity and at least said electrode line is formed.

2. The method of claim 1 , wherein said peripheral electrodes are formed by:

depositing a conformal conductive layer on said dielectric spacer; and

patterning said conformal conductive layer into said peripheral electrodes.

3. The method of claim 2 , wherein said patterning of said conformal conductive layer comprises:

forming a photoresist layer over said conformal conductive layer;

patterning said photoresist layer such that a remaining portion of said photoresist layer straddles said electrode line; and

performing an anisotropic etch on said conformal conductive layer employing said patterned photoresist layer as an etch mask.

4. The method of claim 3 , wherein remaining portions of said conformal conductive layer after said anisotropic etch include:

portions of said conformal conductive layer underneath said photoresist layer; and

vertical portions of said conformal conductive layer that are not covered by the lithographically patterned photoresist layer remain after said anisotropic etching.

5. The method of claim 3 , further comprising removing a portion of said conformal conductive layer from above a top surface of said electrode line after said anisotropic etch, wherein two remaining disjoined portions of said conformal conductive layer constitute said peripheral electrodes.

6. The method of claim 5 , wherein said second dielectric material layer are formed over said conformal conductive layer, and said method further comprises physically exposing a top surface of said portion of said conformal conductive layer by forming a cavity in said conformal conductive layer, wherein said portion of said conformal conductive layer is removed by an etch.

7. The method of claim 6 , further comprising filling said cavity with a dielectric fill material, wherein said dielectric fill material is deposited directly on said electrode line.

8. The method of claim 3 , wherein said remaining portion of said photoresist layer cover horizontal portions of said conformal conductive layer contacting said first dielectric material layer.

9. The method of claim 2 , wherein said conformal conductive layer is deposited directly on a top surface of said electrode line.

10. The method of claim 2 , wherein said conformal conductive layer is deposited directly on outer sidewall surfaces of said dielectric spacer.

11. The method of claim 2 , wherein said conformal conductive layer is deposited directly on a top surface of said first dielectric material layer.

12. A method of forming a sensor structure, said method comprising:

forming a template structure on a first dielectric material layer, wherein template structure comprises:

a uniform width semiconductor region having a uniform width throughout;

a first tapered semiconductor region adjoined to said uniform width semiconductor region at a proximal end thereof and having a first variable width that increases with distance from said uniform width semiconductor region; and

a second tapered semiconductor region adjoined to said uniform width semiconductor region at a proximal end thereof and having a second variable width that increases with distance from said uniform width semiconductor region;

forming an electrode line straddling said template structure;

forming a second dielectric material layer over said template structure; and

removing said template structure selective to said first and second dielectric material layers to form a cavity, wherein a sensor structure comprising said cavity and at least said electrode line is formed.

13. A method of forming a sensor structure, said method comprising:

forming a template structure on a first dielectric material layer,

forming an electrode line straddling said template structure;

forming a dielectric spacer around said electrode line;

forming peripheral electrodes laterally spaced from said electrode line by said dielectric spacer;

forming a second dielectric material layer over said template structure;

forming at least one via cavity through said second dielectric material layer, wherein a surface of said template structure is physically exposed at a bottom of each of said at least one via cavity; and

removing said template structure selective to said first and second dielectric material layers to form a cavity that is contiguously connected to said at least one via cavity, wherein a sensor structure comprising said cavity and at least said electrode line is formed.

14. The method of claim 13 , wherein said peripheral electrodes are formed by:

depositing a conformal conductive layer on said dielectric spacer; and

patterning said conformal conductive layer into said peripheral electrodes.

15. The method of claim 14 , wherein said patterning of said conformal conductive layer comprises:

forming a photoresist layer over said conformal conductive layer;

patterning said photoresist layer such that a remaining portion of said photoresist layer straddles said electrode line; and

performing an anisotropic etch on said conformal conductive layer employing said patterned photoresist layer as an etch mask.

16. The method of claim 15 , wherein remaining portions of said conformal conductive layer after said anisotropic etch include:

portions of said conformal conductive layer underneath said photoresist layer; and

vertical portions of said conformal conductive layer that are not covered by the lithographically patterned photoresist layer remain after said anisotropic etching.

17. The method of claim 15 , further comprising removing a portion of said conformal conductive layer from above a top surface of said electrode line after said anisotropic etch, wherein two remaining disjoined portions of said conformal conductive layer constitute said peripheral electrodes.

18. The method of claim 14 , wherein said conformal conductive layer is deposited directly on a top surface of said first dielectric material layer.

19. The method claim 13 , wherein template structure comprises:

a uniform width semiconductor region having a uniform width throughout;

a first tapered semiconductor region adjoined to said uniform width semiconductor region at a proximal end thereof and having a first variable width that increases with distance from said uniform width semiconductor region; and

a second tapered semiconductor region adjoined to said uniform width semiconductor region at a proximal end thereof and having a second variable width that increases with distance from said uniform width semiconductor region.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2013
From: CHANG, JOSEPHINE B.; GUILLORN, MICHAEL A.; JOSEPH, ERIC A.; PAPA RAO, SATYAVOLU S.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 029561/0448 →
Continuity (1)
Related Publication 20140183667A1 · Jul 3, 2014