Bipolar junction transistor with multiple emitter fingers
Methods for fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.
1. A method of fabricating a bipolar junction transistor, the method comprising:
forming an intrinsic base layer;
forming a plurality of sacrificial emitter pedestals on the intrinsic base layer;
depositing an extrinsic base layer on the intrinsic base layer, the extrinsic base layer in a self-aligned relationship with the sacrificial emitter pedestals;
forming a silicide layer on the extrinsic base layer such that a first portion of the silicide layer bridges a gap between adjacent pairs of the sacrificial emitter pedestals;
removing the sacrificial emitter pedestals to define emitter windows extending through the silicide layer and the extrinsic base layer to the intrinsic base layer; and
forming a plurality of emitters of the bipolar junction transistor with one of the emitters disposed in each of the emitter windows.
2. The method of claim 1 wherein each of the sacrificial emitter pedestals includes a plurality of sidewalls, and further comprising:
before depositing the extrinsic base layer, forming non-conductive spacers on the sidewalls of each of the sacrificial emitter pedestals.
3. The method of claim 2 wherein forming the plurality of emitters comprises:
depositing a layer of a conductive material that fills open space between the non-conductive spacers with a conductor to form the emitters.
4. The method of claim 2 wherein the non-conductive spacers surround the sidewalls of the emitters, and each emitter is in a contacting relationship with a top surface of the intrinsic base layer.
5. The method of claim 1 wherein the intrinsic base layer is formed on a top surface of a device region, the intrinsic base layer includes a raised region that is elevated relative to the top surface of the device region, and the emitters directly contact the top surface on the raised region.
6. The method of claim 5 further comprising:
forming shallow trench isolation regions to define the device region,
wherein the raised region of the intrinsic base layer is circumscribed by the shallow trench isolation regions.
7. The method of claim 1 wherein the emitters are spatially distributed in a first emitter finger and a second emitter finger, and the first portion of the silicide layer is positioned between the first emitter finger and the second emitter finger.
8. The method of claim 7 wherein the first emitter finger includes a first emitter and a second emitter having a first end-to-end arrangement, the second emitter finger includes a third emitter and a fourth emitter having a second end-to-end arrangement, and the first and second emitter fingers are juxtaposed in a side-by-side arrangement.
9. The method of claim 8 wherein the first portion of the silicide layer is positioned between the first and third emitters and is positioned between the second and fourth emitters, and the silicide layer includes a second portion positioned between the first and second emitters and positioned between the third and fourth emitters.
10. The method of claim 7 wherein each of the first and second sacrificial emitter pedestals includes a plurality of sidewalls, and further comprising:
before depositing the extrinsic base layer, forming non-conductive spacers on the sidewalls of each of the sacrificial emitter pedestals,
wherein the first portion of the silicide layer bridges a gap between the non-conductive spacers of the first emitter finger and the non-conductive spacers of the second emitter finger.
11. The method of claim 10 wherein forming the plurality of emitters comprises:
depositing a layer of a conductive material that fills open space between the non-conductive spacers with the conductive material to form the emitters.
12. The method of claim 1 wherein the intrinsic base layer is formed on a top surface of a device region, and
forming a hardmask layer on the intrinsic base layer and having an opening inside which the sacrificial emitter pedestals are located.
13. The method of claim 12 wherein the extrinsic base layer is comprised of a semiconductor material that is deposited by an epitaxial deposition process inside the opening and on the intrinsic base layer without depositing the semiconductor material on the hardmask layer.
14. The method of claim 12 further comprising:
implanting an n-type dopant into the device region to form a collector.