Method and system for determining overlap process windows in semiconductors by inspection techniques
The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished.
1. A method, comprising:
transferring a first pattern of a first layout layer of a semiconductor device into a material layer formed above a first test region and a second test region of a substrate;
transferring a second pattern of a second layout layer of said semiconductor device into said material layer formed above said first test region, said first and second layout layers being spatially correlated to each other so as to define an overlap area;
transferring a geometrically modulated version of said second pattern into said material layer formed above said second test region; and
determining a structural difference in said material layer between said first test region and said second test region so as to assess a process margin with respect to said overlap area.
2. The method of claim 1 , wherein transferring a geometrically modulated version of said second pattern into said material layer formed above said second test region comprises applying a predefined lateral translation of said second pattern relative to said first pattern.
3. The method of claim 1 , wherein transferring a geometrically modulated version of said second pattern into said material layer formed above said second test region comprises providing said geometrically modulated version by using at least some pattern features of said second pattern with a different critical dimension.
4. The method of claim 1 , wherein transferring a geometrically modulated version of said second pattern into said material layer formed above said second test region comprises modifying a lateral dimension of at least some pattern features of said second pattern and applying a predefined lateral translation to said second pattern having said at least some features with a modified lateral dimension.
5. The method of claim 1 , wherein transferring at least one of said first and second patterns into said material layer comprises performing a lithography process and at least one etch process.
6. The method of claim 5 , wherein transferring said first pattern into said material layer comprises performing a first etch process and wherein transferring said second pattern and said geometrically modulated version of said second pattern into said material layer comprises performing a second etch process.
7. The method of claim 6 , wherein said first and second etch processes are performed by using the same process recipe.
8. The method of claim 1 , wherein transferring said first and second patterns and said modulated version of said second pattern comprises performing a sequence of lithography process without an etch process.
9. The method of claim 1 , wherein said material layer is a homogenous material layer.
10. The method of claim 1 , wherein said material layer comprises a first sub-layer and a second sub-layer.
11. The method of claim 1 , wherein determining a structural difference between said first test region and said second test region comprises performing a substrate inspection process.