Silicon controlled rectifier structure with improved junction breakdown and leakage control
Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.
1. A method of fabricating a device structure that includes a silicon controlled rectifier formed in a device region, the method comprising:
forming a section of a gate stack comprised of a plurality of first layers on a top surface of the device region and laterally positioned on the top surface in vertical alignment with a first p-n junction of the silicon controlled rectifier; and
forming a section of a second layer that directly contacts the top surface of the device region and that is laterally positioned on the top surface in vertical alignment with a second p-n junction of the silicon controlled rectifier,
wherein the gate stack is comprised of an electrical conductor and the second layer is comprised of an electrical insulator with a higher electrical resistivity than the electrical conductor.
2. The method of claim 1 wherein the device region is contained in a semiconductor layer of a silicon-on-insulator substrate, and further comprising:
forming a plurality of doped regions having opposite conductivity types in the semiconductor layer and laterally arranged to form the silicon controlled rectifier.
3. The method of claim 2 wherein the silicon-on-insulator substrate includes a buried dielectric layer with a top surface, and the doped regions extend from the top surface of the device region to the top surface of the buried dielectric layer.
4. The method of claim 1 further comprising:
depositing the plurality of first layers on the top surface of the device region; and
patterning the first layer to form the section of the gate stack.
5. The method of claim 4 further comprising:
depositing the second layer on the top surface of the device region and on the section of the first layer; and
patterning the second layer to form the section of the second layer.
6. The method of claim 1 further comprising:
forming a first well having a first conductivity type in the device region; and
forming a second well having a second conductivity type opposite to the first conductivity type in the device region,
wherein the second p-n junction is defined between the first well and the second well.
7. The method of claim 6 further comprising:
forming an anode having the second conductivity type in the device region;
forming a cathode having the first conductivity type in the device region and laterally separated from the anode by the first well and the second well,
wherein the first p-n junction is defined between the anode and the first well or between the cathode and the second well.
8. The method of claim 1 further comprising:
forming a first well having a first conductivity type in the device region; and
forming an anode having a second conductivity type opposite to the first conductivity type and laterally arranged relative to the first well so that the second p-n junction is defined between the first well and the anode.
9. The method of claim 8 further comprising:
forming a second well having the second conductivity type and laterally arranged relative to the first well so that the first p-n junction is defined between the first well and the second well.
10. The method of claim 1 further comprising:
forming a first well having a first conductivity type in the device region;
forming a second well having a second conductivity type opposite to the first conductivity type in the device region; and
forming a cathode having the first conductivity type in the device region and laterally arranged relative to the second well so that the second p-n junction is defined between the cathode and the second well.
11. The method of claim 10 wherein the first p-n junction is defined between the first well and the second well.
12. A method of fabricating a device structure that includes a silicon controlled rectifier formed in a device region, the method comprising:
forming a section of a first layer on a top surface of the device region and laterally positioned on the top surface in vertical alignment with a first p-n junction of the silicon controlled rectifier; and
forming a section of a second layer on the top surface of the device region and laterally positioned on the top surface in vertical alignment with a second p-n junction of the silicon controlled rectifier,
wherein the first layer is comprised of a first material and the second layer is comprised of a second material with a higher electrical resistivity than the first material, the first section of the first layer has a first edge, and the second section of the second layer has a first edge that is coextensive with the first edge of the first section of the first layer.
13. The method of claim 12 wherein the second layer partially overlaps the first section of the first layer so that the first edge of the first section of the first layer is covered.
14. The method of claim 12 wherein the first layer has a second section positioned on the top surface of the device region and separated from the first section of the first layer by the section of the second layer, the silicon controlled rectifier includes a third p-n junction in the device region, and the second section of the first layer is in vertical alignment with the third p-n junction.
15. The method of claim 12 wherein the first layer has a second section positioned on the top surface of the device region and separated from the first section of the first layer by the section of the second layer, the section of the second layer has a second edge, and the second section of the first layer has a second edge that is coextensive with the second edge of the section of the second layer.
16. The method of claim 12 wherein the first layer has a second section positioned on the top surface of the device region and separated from the first section of the first layer by the section of the second layer, the second section of the first layer and the first section of the first layer are separated by a gap, and the section of the second layer is positioned in the gap.
17. The method of claim 12 wherein the first section of the first layer has a second edge, and the first p-n junction is laterally positioned between the first edge of the first section of the first layer and the second edge of the first section of the first layer.
18. The method of claim 12 wherein the section of the second layer has a second edge, and the second p-n junction is laterally positioned between the first edge of the section of the second layer and the second edge of the section of the second layer.
19. The method of claim 12 wherein the second material is an electrical insulator, and the first material is an electrical conductor.
20. The method of claim 12 wherein the second material is silicon nitride, and the first material is doped polysilicon.