Transistor device with improved source/drain junction architecture and methods of making such a device
One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.
1. A method, comprising:
forming an isolation region in a semiconductor substrate so as to define an active region in said substrate;
forming a gate structure above said active region; and
after forming said gate structure, forming a plurality of halo implant regions in said active region, wherein an outer edge of each of said halo implant regions is laterally spaced apart from an adjacent inner edge of said isolation region, wherein forming said plurality of halo implant region comprises:
forming a patterned halo implantation mask that has an opening that exposes said gate structure and a portion, but not all, of said active region positioned between said gate structure and said isolation region; and
performing a plurality of angled ion implantation processes through said patterned halo implantation mask to form said plurality of halo implant regions.
2. The method of claim 1 , further comprising;
performing an extension ion implantation process through said patterned halo implantation mask so as to form a plurality of extension implant regions in said substrate, wherein an outer edge of each of said extension implant regions is laterally spaced apart from an adjacent inner edge of said isolation region.
3. The method of claim 2 , further comprising;
removing said patterned halo implantation mask;
forming at least one sidewall spacer adjacent said gate structure;
after forming said at least one sidewall spacer, forming a patterned source/drain implantation mask above said active region; and
performing a source/drain ion implantation process through said patterned source/drain implantation mask so as to form a plurality of deep source/drain implant regions in said substrate, each of said deep source/drain implant regions having first and second portions, said first portion being positioned above a corresponding halo implant region, said second portion being positioned adjacent said isolation region and above a portion of said active region where said corresponding halo implant region is absent.
4. The method of claim 1 , further comprising performing an anneal process on said substrate.
5. The method of claim 1 , wherein said patterned halo implantation mask is formed such that a space between an inner edge of said opening and said gate structure has a lateral width that is equal to 2-3 times an overall height of said gate structure.
6. The method of claim 2 , wherein said halo implant regions are formed prior to forming said extension implant regions.
7. The method of claim 2 , wherein said extension implant regions are formed prior to forming said halo implant regions.
8. A method, comprising:
forming an isolation region in a semiconductor substrate so as to define an active region in said substrate;
forming a gate structure above said active region;
after forming said gate structure, forming a patterned halo implantation mask that has an opening that exposes said gate structure and a portion, but not all, of said active region positioned between said gate structure and said isolation region; and
performing a plurality of angled ion implantation processes through said patterned halo implantation mask to form a plurality of halo implant regions in said substrate.
9. The method of claim 8 , wherein an outer edge of each of said halo implant regions is laterally spaced apart from an adjacent inner edge of said isolation region.
10. The method of claim 8 , wherein said patterned halo implantation mask is formed such that a space between an inner edge of said opening and said gate structure has a lateral width that is equal to 2-3 times an overall height of said gate structure.
11. The method of claim 8 , further comprising;
performing an extension ion implantation process through said patterned halo implantation mask so as to form a plurality of extension implant regions in said substrate.
12. The method of claim 11 , wherein an outer edge of each of said extension implant regions is laterally spaced apart from an adjacent inner edge of said isolation region.
13. The method of claim 12 , wherein an outer edge of each of said halo implant regions is laterally spaced apart from an adjacent inner edge of said isolation region.
14. The method of claim 11 , wherein said halo implant regions are formed prior to forming said extension implant regions.
15. The method of claim 11 , wherein said extension implant regions are formed prior to forming said halo implant regions.
16. A method, comprising:
forming an isolation region in a semiconductor substrate so as to define an active region in said substrate;
forming a gate structure above said active region;
after forming said gate structure, forming a patterned halo implantation mask that has an opening that exposes said gate structure and a portion, but not all, of said active region positioned between said gate structure and said isolation region;
performing a plurality of angled ion implantation processes through said patterned halo implantation mask to form a plurality of halo implant regions in said substrate, wherein an outer edge of each of said halo implant regions is laterally spaced apart from an adjacent inner edge of said isolation region; and
performing an extension ion implantation process through said patterned halo implantation mask so as to form a plurality of extension implant regions in said substrate, wherein an outer edge of each of said extension implant regions is laterally spaced apart from said adjacent inner edge of said isolation region.
17. The method of claim 16 , further comprising;
removing said patterned halo implantation mask;
forming at least one sidewall spacer adjacent said gate structure;
after forming said at least one sidewall spacer, forming a patterned source/drain implantation mask above said active region; and
performing a source/drain ion implantation process through said patterned source/drain implantation mask so as to form a plurality of deep source/drain implant regions in said substrate, each of said deep source/drain implant regions having first and second portions, said first portion being positioned above a corresponding halo implant region, said second portion being positioned adjacent said isolation region and above a portion of said active region where said corresponding halo implant region is absent.
18. The method of claim 16 , further comprising performing an anneal process on said substrate.
19. The method of claim 16 , wherein said halo implant regions are formed prior to forming said extension implant regions.
20. The method of claim 16 , wherein said extension implant regions are formed prior to forming said halo implant regions.