Integrated circuit having MOSFET with embedded stressor and method to fabricate same
A structure includes a gate stack or gate stack precursor disposed on a SOI layer disposed upon a BOX that is disposed upon a surface of a crystalline semiconductor substrate. A transistor channel is disposed within the SOI layer. The structure further includes a channel stressor layer disposed at least partially within a recess in the substrate and disposed about the channel, and a layer of crystalline dielectric material disposed between the stressor layer and a surface of the substrate.
1. A structure, comprising:
a transistor gate stack disposed on a semiconductor-on-insulator (SOI) layer that in turn is disposed upon a buried oxide layer disposed upon a surface of a crystalline semiconductor substrate, where a transistor channel is disposed within the SOI layer;
a channel stressor layer disposed at least partially within a recess formed in the crystalline semiconductor substrate and disposed about the channel; and
a layer of crystalline dielectric material disposed between the channel stressor layer and a surface of the crystalline semiconductor substrate;
where the layer of crystalline dielectric material is an epitaxial layer disposed on an exposed portion of the surface of the crystalline semiconductor substrate only at the bottom of the recess.
2. The structure of claim 1 , where the recess has substantially vertical sidewall surfaces, and where the exposed surface is at least a bottom surface of the recess that is substantially perpendicular to the vertical sidewall surfaces.
3. The structure of claim 1 , where the recess comprises at least one sidewall that extends at an angle upwardly towards and at least partially beneath the transistor channel, and where the exposed surface is at least along the at least one upwardly angled sidewall.
4. The structure of claim 1 , where the layer of crystalline dielectric material is comprised of a rare earth oxide or a combination of rare earth oxides.
5. The structure of claim 1 , where the layer of crystalline dielectric material is comprised of a Perovskite.
6. The structure of claim 1 , where the layer of crystalline dielectric material is comprised of an aluminum oxide or an aluminum oxide compound.
7. The structure of claim 1 , where the channel stressor material is comprised of one of silicon, germanium, silicon germanium, carbon doped silicon, a silicon-germanium alloy and a compound semiconductor material.
8. The structure of claim 1 , where an edge of the recess is spaced away from the gate stack by a width of a spacer disposed adjacent to the buried oxide layer, and where the channel stressor material substantially fills the recess and extends over the spacer to a thickness that at least covers the SOI layer.
9. The structure of claim 1 , where the gate stack is comprised of a gate stack precursor structure, and where an edge of the recess is spaced away from the gate stack precursor structure by a width of a spacer disposed adjacent to the buried oxide layer, and where the channel stressor material substantially fills the recess and extends over the spacer to a thickness that at least covers the SOI layer.
10. The structure of claim 1 , where the layer of crystalline dielectric material has a thickness in a range of about 2 nm to about 10 nm.
11. The structure of claim 1 , where the layer of crystalline dielectric material has a thickness of about 5 nm.
12. A structure, comprising:
a transistor gate stack disposed on a semiconductor-on-insulator (SOI) layer that in turn is disposed upon a buried oxide layer disposed upon a surface of a crystalline semiconductor substrate, where a transistor channel is disposed within the SOI layer;
a channel stressor layer disposed at least partially within a recess formed in the crystalline semiconductor substrate and disposed about the channel; and
a layer of crystalline dielectric material disposed between the channel stressor layer and a surface of the crystalline semiconductor substrate;
where sidewalls of the gate stack are surrounded with a spacer layer having an inner surface and a second opposite surface, where the recess has a first surface that is a substantially vertical sidewall surface, a second surface that extends from a bottom edge of the first surface at an angle upwardly towards to a first point beneath the transistor channel, and a third surface that extends from the first point at an angle upwardly to a second point beneath the second surface of the spacer layer.
13. The structure of claim 12 , where the layer of crystalline dielectric material is disposed upon at least the second surface of the recess.