Lateral diffusion metal oxide semiconductor (LDMOS)

1. A device, comprising:

a semiconductor substrate having a top surface and a configuration of features, a portion of said features having a height above said top surface of said semiconductor substrate;

a first conformal dielectric layer on said top surface of said semiconductor substrate and on said portion of said features above said top surface;

a conformal etch-stop layer on said first conformal dielectric layer;

a second conformal dielectric layer on said conformal etch-stop layer, said second conformal dielectric layer having a planarized surface above, relative to said top surface, said conformal etch-stop layer; and

electrodes in said second conformal dielectric layer and on said conformal etch-stop layer, thicknesses of said electrodes being determined by said height of said features below said electrodes.

2. The device according to claim 1 , said first conformal dielectric layer conforming to said portion of said features having a height above said top surface and comprising a mesa above, relative to said top surface, said portion of said features; and

said conformal etch-stop layer and said second conformal dielectric layer having said mesa.

3. The device according to claim 1 , said semiconductor substrate further comprising:

a source region;

a drain region; and

a gate conductor having a height above said top surface of said semiconductor substrate; and

said device further comprising:

metalized contact studs extending through said first conformal dielectric layer, said conformal etch-stop layer, and said second conformal dielectric layer, said metalized contact studs comprising:

a source contact stud connected to said source region,

a drain contact stud connected to said drain region, and

a gate contact stud connected to said gate conductor.

4. The device according to claim 3 , said electrodes comprising:

a source electrode on said conformal etch-stop layer and contacting said source contact stud;

a gate electrode on said conformal etch-stop layer and contacting said gate contact stud; and

a drain electrode on said conformal etch-stop layer and contacting said drain contact stud.

5. The device according to claim 1 , further comprising trenches in said second conformal dielectric layers, said electrodes being in said trenches.

6. The device according to claim 1 , further comprising a plurality of conformal dielectric layers; and

a plurality of conformal etch-stop layers embedded between successive ones of said conformal dielectric layers.

7. A lateral diffusion metal oxide semiconductor (LDMOS), comprising:

a semiconductor substrate comprising:

a shallow trench isolation (STI) structure in a top surface of said substrate;

a drift region in said substrate below, relative to said top surface, said STI structure; and

a source region and a drain region in said substrate and on opposite sides of said STI structure, said source region being spaced from said STI structure by a gap;

a gate conductor over said substrate over, relative to said top surface, said gap between said STI structure and said source region, said gate conductor partially overlapping said drift region;

a conformal dielectric layer on said top surface of said substrate and on said gate conductor;

a conformal etch-stop layer embedded within said conformal dielectric layer, said conformal dielectric layer having a planarized surface above, relative to said top surface, said conformal etch-stop layer; and

a drift electrode on said conformal etch-stop layer over, relative to said top surface, said drift region, lateral boundaries of said drift electrode being within lateral boundaries of said STI structure.

8. The LDMOS according to claim 7 , said conformal dielectric layer conforming to said gate conductor and comprising a mesa above, relative to said top surface, said gate conductor; and

said conformal etch-stop layer having said mesa.

9. The LDMOS according to claim 7 , further comprising:

metalized contact studs extending through said conformal dielectric layer and said conformal etch-stop layer, said metalized contact studs comprising:

a source contact stud connected to said source region,

a gate contact stud connected to said gate conductor, and

a drain contact stud connected to said drain region; and

electrode conductors comprising:

a source electrode on said conformal etch-stop layer and contacting said source contact stud,

a gate electrode on said conformal etch-stop layer and contacting said gate contact stud, and

a drain electrode on said conformal etch-stop layer and contacting said drain contact stud.

10. The LDMOS according to claim 9 , further comprising trenches in said conformal dielectric layer, said electrode conductors being in said trenches.

11. The LDMOS according to claim 7 , further comprising:

gate pieces over said substrate over, relative to said top surface, said STI structure,

said conformal dielectric layer conforming to said gate conductor and said gate pieces, and comprising a mesa above, relative to said top surface, said gate conductor and said gate pieces.

12. The LDMOS according to claim 7 , further comprising a plurality of conformal etch-stop layers embedded in said conformal dielectric layer.

13. A method, comprising:

providing a substrate of semiconductor material, said substrate having a top surface;

forming a feature on said substrate, said feature having a height above said top surface of said substrate;

depositing a first conformal dielectric layer on said top surface of said substrate and on said feature above said top surface;

depositing a conformal etch-stop layer on said first conformal dielectric layer;

depositing a second conformal dielectric layer on said conformal etch-stop layer;

performing a material removal process on said second conformal dielectric layer, said material removal process stopping above, relative to said top surface, said etch-stop layer; and

forming an electrode in said second conformal dielectric layer and on said conformal etch-stop layer, a thickness of said electrode being determined by said height of said feature on said substrate below said electrode.

14. The method according to claim 13 , said depositing a first conformal dielectric layer on said top surface of said substrate and on said feature further comprising forming a mesa in said first conformal dielectric layer above, relative to said top surface, said feature; and

said conformal etch-stop layer and said second conformal dielectric layer having said mesa.

15. The method according to claim 13 , further comprising:

forming a semiconducting drift region in said substrate;

forming a shallow trench isolation (STI) structure in said top surface of said substrate, said STI structure being formed over, relative to said top surface, said drift region;

forming a source region and a drain region in said substrate on opposite sides of said STI structure, said source region being spaced from said STI structure by a gap; and

forming a gate conductor on said substrate over, relative to said top surface, said gap between said STI structure and said source region, said gate conductor partially overlapping said drift region.

16. The method according to claim 15 , further comprising:

extending metalized contact studs through said first conformal dielectric layer, said conformal etch-stop layer, and said second conformal dielectric layer, said metalized contact studs comprising:

a source contact stud connected to said source region,

a gate contact stud connected to said gate conductor, and

a drain contact stud connected to said drain region; and

patterning an electrode conductor on said etch-stop layer to form:

a source electrode contacting said source contact stud,

a gate electrode contacting said gate contact stud,

a drain electrode contacting said drain contact stud, and

a drift electrode over, relative to said top surface, said drift region, a thickness of each of said source electrode, said gate electrode, said drain electrode, and said drift electrode being determined by a height of a structure below said source electrode, said gate electrode, said drain electrode, and said drift electrode, respectively.

17. The method according to claim 16 , said patterning an electrode conductor comprising one of:

patterning a trench in said second conformal dielectric layer using selective reactive ion etching (RIE), said selective RIE stopping on said etch-stop layer, and

patterning a trench in said second conformal dielectric layer using non-selective reactive ion etching; and

forming an electrode conductor in said trench.

18. The method according to claim 17 , said forming an electrode conductor in said trench comprising using a damascene metallization process.

19. The method according to claim 15 , further comprising:

forming gate pieces on said substrate over, relative to said top surface, said STI structure,

said first conformal dielectric layer conforming to said gate conductor and said gate pieces, and forming a mesa above, relative to said top surface, said gate conductor and said gate pieces.

20. The method according to claim 13 , further comprising:

prior to performing said material removal process, depositing an additional conformal etch-stop layer on said second conformal dielectric layer; and

depositing an additional conformal dielectric layer on said additional conformal etch-stop layer.