Fin isolation in multi-gate field effect transistors

1. A method for fabricating a field effect transistor (FET) device, the method comprising: forming a plurality of semiconductor fins on a substrate, wherein each semiconductor fin of the plurality of semiconductor fins includes a hardmask layer disposed thereon; depositing a sacrificial layer over exposed portions of the substrate and the hard mask layer; removing portions of the sacrificial layer to expose the hard mask layer; completely removing at least one semiconductor fin of the plurality of semiconductor fins from a portion of the substrate to form a cavity partially defined by the sacrificial layer; increasing a width of the cavity; filling the cavity with a dielectric material to form an isolation fin on the portion of the substrate such that a width of the isolation fin is greater than a width of at least one semiconductor fin of the plurality of semiconductor fins; and forming a gate stack over the plurality of semiconductor fins and the isolation fin.

2. The method of claim 1 , wherein the hardmask layer includes a nitride material.

3. The method of claim 1 , wherein the forming the isolation fin comprises depositing a layer of the dielectric material over the hardmask layer, the sacrificial layer, and in the cavity.

4. The method of claim 3 , wherein the method further comprises removing portions of the layer of the dielectric material to expose the hardmask layer.

5. The method of claim 4 , wherein the method further comprises removing the sacrificial layer.

6. The method of claim 4 , wherein the method further comprises removing portions of the layer of the dielectric material and portions of the sacrificial layer to expose portions the plurality of semiconductor fins.

7. A method for fabricating a field effect transistor (FET) device, the method comprising:

patterning a first semiconductor fin, a second semiconductor fin, and a third semiconductor fin on a substrate, the second semiconductor fin arranged between the first semiconductor fin and the third semiconductor fin, the first semiconductor fin, the second semiconductor fin and the third semiconductor fin having a hardmask layer disposed thereon;

depositing a sacrificial layer over exposed portions of the substrate and the hardmask layer;

removing portions of the sacrificial layer to expose portions of the hardmask layer;

removing the hardmask layer disposed on the second semiconductor fin and completely removing the second semiconductor fin to form a cavity; increasing a width of the cavity followed by

depositing a dielectric material in the cavity;

removing the sacrificial layer to define an isolation fin that includes the dielectric material in the cavity, and expose the first semiconductor fin and the third semiconductor fin; wherein a width of the isolation fin is larger than that of a width of the first and third semiconductor fins; and

forming a gate stack over a portion of the first semiconductor fin, the isolation fin, and the third semiconductor fin.

8. The method of claim 7 , wherein the hardmask layer includes a nitride material.

9. The method of claim 7 , wherein the sacrificial layer includes an oxide material.

10. The method of claim 7 , wherein the depositing the dielectric material in the cavity includes depositing a layer of the dielectric material over the hardmask layer, the sacrificial layer, and in the cavity.

11. The method of claim 10 , wherein prior to removing the sacrificial layer to define the isolation fin, the method comprises removing portions of the layer of the dielectric material to expose the hardmask layer.

12. The method of claim 10 , wherein prior to removing the sacrificial layer to define the isolation fin, the method comprises:

removing portions of the layer of the dielectric material to expose the hardmask layer; and

removing portions of the sacrificial layer, the dielectric material, and the hardmask layer to expose a portion of the first semiconductor fin and a portion of the second semiconductor fin.

13. The method of claim 7 , wherein the forming the gate stack comprises:

patterning a dummy gate stack over portions of the first semiconductor fin, the isolation fin, and the third semiconductor fin;

forming active regions over portions of the first semiconductor fin and the third semiconductor fin;

removing the dummy gate stack to expose channel regions of the first semiconductor fin and the third semiconductor fin; and

forming the gate stack.

14. A method for fabricating a field effect transistor (FET) device, the method comprising:

forming a plurality of semiconductor fins on a substrate;

completely removing at least one semiconductor fin of the plurality of semiconductor fins from a portion of the substrate;

forming an isolation fin that includes a dielectric material on the portion of the substrate, the isolation fin having a trapezoidal shape with sloped sidewalls arranged at an oblique angle relative to a planar surface of the substrate; and

forming a gate stack over the plurality of semiconductor fins and the isolation fin.

15. A method for fabricating a field effect transistor (FET) device, the method comprising:

forming a plurality of semiconductor fins on a substrate, wherein adjacent pairs of semiconductor fins are initially connected to one another by distal ends of semiconductor material;

completely removing at least one semiconductor fin of the plurality of semiconductor fins from a portion of the substrate, and removing the distal ends of semiconductor material so as to isolate the adjacent pairs of semiconductor fins from one another;

forming at least one isolation fin that includes a dielectric material on the portion of the substrate, wherein the dielectric material also replaces the distal ends of semiconductor material with distal ends of the dielectric material; and

forming a gate stack over the plurality of semiconductor fins and the isolation fin.