Multi-layer input/output pad ring for solid state device controller
View Patent ↗Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory devices, a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit, and a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads includes a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal.
1. An integrated circuit comprising:
a solid state device controller configured to control a plurality of flash memory devices;
a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit; and
a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads comprises a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal.
2. The integrated circuit of claim 1 , wherein the second set of IO pads are arranged as a second pad ring concentric with the first pad ring, and wherein an area encompassed by the second pad ring is smaller than an area encompassed by the first pad ring.
3. The integrated circuit of claim 2 , wherein each of the first set of IO pads comprises a power source node and a ground node.
4. The integrated circuit of claim 3 , wherein the ground node of one of the first set of IO pads is electrically coupled to the ground node of every other IO pads in the first set.
5. The integrated circuit of claim 4 , wherein each of the second set of IO pads comprises a power source node and a ground node.
6. The integrated circuit of claim 5 , wherein the ground node of one of the second set of IO pads is electrically coupled to the ground node of every other IO pads in the second set.
7. The integrated circuit of claim 6 , wherein the ground node of one of the first set of IO pads is electrically coupled to the ground node of one of the second set of IO pads.
8. The integrated circuit of claim 6 , wherein one of the first set of IO pads comprises a first electrostatic discharge protection circuit coupled to the power source node and the ground node of the one of the first set of IO pads, and wherein one of the second set of IO pads comprises a second electrostatic discharge protection circuit coupled to the power source node and the ground node of the one of the second set of IO pads.
9. The integrated circuit of claim 6 , wherein the first electrostatic discharge protection circuit is electrically coupled to the second electrostatic discharge protection circuit.
10. The integrated circuit of claim 6 , wherein the first electrostatic discharge protection circuit is electrically decoupled to the second electrostatic discharge protection circuit.
11. A solid state device comprising:
a plurality of NAND flash memory devices;
an integrated circuit comprising:
a solid state device controller configured to control the plurality of NAND flash memory devices; and
a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit; and
a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads comprises a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal.
12. The solid state device of claim 11 , wherein the second set of IO pads are arranged as a second pad ring concentric with the first pad ring, and wherein an area encompassed by the second pad ring is smaller than an area encompassed by the first pad ring.
13. The solid state device of claim 12 , wherein each of the first set of IO pads comprises a power source node and a ground node.
14. The solid state device of claim 13 , wherein the ground node of one of the first set of IO pads is electrically coupled to the ground node of every other IO pads in the first set.
15. The solid state device of claim 14 , wherein each of the second set of IO pads comprises a power source node and a ground node.
16. The solid state device of claim 15 , wherein the ground node of one of the second set of IO pads is electrically coupled to the ground node of every other IO pads in the second set.
17. The solid state device of claim 16 , wherein the ground node of one of the first set of IO pads is electrically coupled the ground node of one of the second set of IO pads.
18. The solid state device of claim 16 , wherein one of the first set of IO pads comprises a first electrostatic discharge protection circuit coupled to the power source node and the ground node of the one of the first set of IO pads, and wherein one of the second set of IO pads comprises a second electrostatic discharge protection circuit coupled to the power source node and the ground node of the one of the second set of IO pads.
19. The solid state device of claim 16 , wherein the first electrostatic discharge protection circuit is electrically coupled to the second electrostatic discharge protection circuit.
20. The solid state device of claim 16 , wherein the first electrostatic discharge protection circuit is electrically decoupled to the second electrostatic discharge protection circuit.