Replacement gate integration scheme employing multiple types of disposable gate structures

1. A method of forming a semiconductor structure comprising:

forming a first disposable gate stack structure comprising a first disposable gate material portion and a second disposable gate stack structure comprising a second disposable gate material portion in a first device region and in a second device region, respectively, on a semiconductor substrate, wherein said forming said first disposable gate stack structure and said second disposable gate stack structure comprises providing a first disposable gate material layer in said first device region and a second disposable gate material layer in said second device region, wherein one of said first disposable gate material layer or said second disposable gate material layer has a protruding portion, performing a touch-up planarization process to remove said protruding portion and to provide said first disposable gate material layer and said second disposable gate material layer with topmost surfaces that are coplanar to each other, and patterning said first disposable gate material layer and said second disposable gate material layer to provide said first disposable gate material portion and said second disposable gate material portion;

depositing a planarization dielectric layer over said first and second disposable gate stack structures;

physically exposing top surfaces of said first and second disposable gate stack structures by planarizing said planarization dielectric layer;

replacing said first disposable gate stack structure with a first replacement gate stack structure employing a step of removing said first disposable gate stack through a simultaneous exposure of said first disposable gate structure and said second disposable gate structure to a same etch chemistry in an etch process, wherein at least a predominant portion of said second disposable gate stack structure remains within said planarization dielectric layer after said etch process; and

replacing said second disposable gate stack structure with a second replacement gate stack structure while said first replacement gate stack structure remains within said planarization dielectric layer.

2. A method of forming a semiconductor structure comprising:

forming a first disposable gate stack structure comprising a first disposable gate material portion and a second disposable gate stack structure comprising a second disposable gate material portion in a first device region and in a second device region, respectively, on a semiconductor substrate, wherein said forming said first disposable gate stack structure and said second disposable gate stack structure comprises providing a first disposable gate material layer in said first device region and a second disposable gate material layer in said second device region, wherein one of said first disposable gate material layer or said second disposable gate material layer has a protruding portion, performing a touch-up planarization process to remove said protruding portion and to provide said first disposable gate material layer and said second disposable gate material layer with topmost surfaces that are coplanar to each other, and patterning said first disposable gate material layer and said second disposable gate material layer to provide said first disposable gate material portion and said second disposable gate material portion;

depositing a planarization dielectric layer over said first and second disposable gate stack structures;

physically exposing top surfaces of said first and second disposable gate stack structures by planarizing said planarization dielectric layer;

replacing said first disposable gate stack structure with a first replacement gate stack structure at least a predominant portion of said second disposable gate stack structure remains within said planarization dielectric layer; and

replacing said second disposable gate stack structure with a second replacement gate stack structure while said first replacement gate stack structure remains within said planarization dielectric layer, wherein said first disposable gate stack structure includes a portion having a composition that is different from any composition that is present within said second disposable gate stack structure.

3. The method of claim 1 , wherein said second disposable gate material portion has a different composition than said first disposable gate material portion.

4. The method of claim 3 , wherein said first disposable gate material portion is removed at an etch rate that is at least 3 times greater than an etch rate of said second disposable gate material portion under said same etch chemistry in said etch process.

5. The method of claim 3 , wherein said first disposable gate material portion is removed at an etch rate that is at least 10 times greater than an etch rate of said second disposable gate material portion under said same etch chemistry in said etch process.

6. The method of claim 3 , wherein said first disposable gate material portion comprises a first semiconductor material, and said second disposable gate material portion comprises a second semiconductor material.

7. The method of claim 6 , wherein said first semiconductor material comprises a first semiconductor material, and said second semiconductor material comprises a second semiconductor material that is different from said first semiconductor material.

8. The method of claim 6 , wherein one of said first semiconductor material and said second semiconductor material comprises an elemental semiconductor material, and another of said first semiconductor material and said second semiconductor material comprises a compound semiconductor material.

9. The method of claim 6 , wherein one of said first semiconductor material and said second semiconductor material comprises a semiconductor material, and another of said first semiconductor material and said second semiconductor material comprises a metallic material.

10. The method of claim 1 , further comprising forming a disposable gate dielectric layer on a surface of said semiconductor substrate prior to forming said first disposable gate material layer, wherein said first disposable gate stack structure comprises a first portion of said disposable gate dielectric layer and said second disposable gate stack structure comprises a second portion of said disposable gate dielectric layer.

11. The method of claim 1 , wherein said first disposable gate material layer is deposited in said first and second device regions simultaneously, and said method further comprises removing a portion of said first disposable gate material layer from said second device region.

12. The method of claim 11 , wherein said second disposable gate material layer is deposited in said first and second device regions simultaneously, and said method further comprises removing a portion of said second disposable gate material layer from said first device region.

13. The method of claim 1 , further comprising:

depositing a hard mask layer over one of said first and second disposable gate material layers; and

patterning said hard mask layer to remove a portion of said hard mask layer from one of said first and second device regions, wherein another of said first and second disposable gate material layers is formed over a patterned portion of said hard mask layer.

14. The method of claim 13 , further comprising:

removing a portion of said another of said first and second disposable gate material layers by planarization employing said patterned portion of said hard mask layer as a stopping layer; and

removing said patterned portion of said hard mask layer.

15. The method of claim 1 , further comprising:

forming a first gate spacer around said first disposable gate stack structure prior to depositing said planarization dielectric layer; and

forming a second gate spacer around said second disposable gate stack structure prior to depositing said planarization dielectric layer.

16. The method of claim 1 , wherein a top surface of said second disposable gate stack structure is coplanar with a top surface of said planarization dielectric layer after formation of said first replacement gate stack structure.

17. A method of forming a semiconductor structure comprising:

forming a first disposable gate stack structure comprising a first disposable gate material portion and a second disposable gate stack structure comprising a second disposable gate material portion in a first device region and in a second device region, respectively, on a semiconductor substrate, wherein said forming said first disposable gate stack structure and said second disposable gate stack structure comprises providing a first disposable gate material layer in said first device region and a second disposable gate material layer in said second device region, wherein one of said first disposable gate material layer or said second disposable gate material layer has a protruding portion, performing a touch-up planarization process to remove said protruding portion and to provide said first disposable gate material layer and said second disposable gate material layer with topmost surfaces that are coplanar to each other, and patterning said first disposable gate material layer and said second disposable gate material layer to provide said first disposable gate material portion and said second disposable gate material portion;

depositing a planarization dielectric layer over said first and second disposable gate stack structures;

physically exposing top surfaces of said first and second disposable gate stack structures by planarizing said planarization dielectric layer;

replacing said first disposable gate stack structure with a first replacement gate stack structure at least a predominant portion of said second disposable gate stack structure remains within said planarization dielectric layer; and

replacing said second disposable gate stack structure with a second replacement gate stack structure while said first replacement gate stack structure remains within said planarization dielectric layer,

wherein a top surface of said second disposable gate stack structure is recessed relative to a top surface of said planarization dielectric layer after removal of said first disposable gate stack structure.

18. The method of claim 17 , wherein a material portion comprising a same material as a conductive material within said first replacement gate stack structure is formed above a remaining portion of said second disposable gate stack structure and below a horizontal plane of a top surface of said planarization dielectric layer after formation of said first replacement gate stack structure.