Semiconductor device including finfet and diode having reduced defects in depletion region
View Patent ↗A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region.
1. A method of fabricating a semiconductor device, the method comprising:
depositing a masking layer on at least one semiconductor fin formed on a first substrate portion of the semiconductor device;
forming a planar substrate on a second substrate portion located a distance away from the first substrate portion, the planar substrate including an active semiconductor region and a doped region on top of the active semiconductor region;
forming an oxide layer on the masking layer and on the active semiconductor region;
forming a resist layer on the oxide layer disposed on the planar substrate;
removing a portion of the resist layer from the oxide layer of the first substrate portion and etching the oxide layer disposed on the masking layer such that the first substrate portion excludes the oxide layer and the second substrate portion includes the oxide layer;
removing the masking layer from the first substrate portion to expose the at least one semiconductor fin;
removing the resist layer and forming a polycrystalline layer on the at least one semiconductor fin located at the first substrate portion and on the oxide layer located at the second substrate portion such that the oxide layer is interposed between the polycrystalline layer and the planar substrate;
patterning the polycrystalline layer to form at least one gate on the at least one fin while protecting the planar substrate from the patterning via the oxide layer; and
implanting ions in the doped region of the planar substrate to form a diode.
2. The method of claim 1 , wherein the implanting ions further comprises implanting first ions having a first polarity at a first area of the doped region and implanting second ions having a second polarity opposite the first polarity at a second area of the doped region.
3. The method of claim 2 , wherein the first and second areas are separated by one another by a depletion area, the depletion area vertically aligned with the polycrystalline material formed on the oxide layer.
4. The method of claim 1 , wherein the oxide layer has a thickness ranging from 15 nanometers to 30 nanometers.
5. The method of claim 1 , wherein the oxide layer is a continuous oxide layer extending from the first substrate portion to the second substrate portion.