IP Library Granted Patent US 9,077,195
Granted Patent B2
US 9,077,195 · App. 13/430,237 · Granted Jul 7, 2015

Input-output circuit

Inventors: Atsushi Wada (Ogaki, JP); Hajime Mizukami (Gifu, JP); Mitsuaki Hatakeyama (Gifu-ken, JP); Shigeto Kobayashi (Gifu-ken, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H02J7/0055H02J2007/0001
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Quick Facts
Patent No.
US 9,077,195
App. No.
13/430,237
Granted
Jul 7, 2015
Kind
B2
Abstract

A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit specifies the kind of charger by detecting the voltages of a DP terminal and a DM terminal. The charger detection circuit detects open, pull-up, pull-down of at least one of the DP terminal and the DM terminal or formation of a short circuit between both the terminals.

Claims (18)

1. An input-output circuit that connects a connector including: at least a power supply terminal; and a first data terminal and a second data terminal, which are data terminals of a differential pair, and an internal circuit to each other, the input-output circuit comprising:

a power supply detection circuit that detects power feeding to the power supply terminal from the outside; and

a charger detection circuit that specifies the kind of charger by detecting voltages of the first data terminal and the second data terminal, wherein the charger detection circuit detects open, pull-up, pull-down of at least one of the first data terminal and the second data terminal, or formation of a short circuit between both the terminals, wherein the charger detection circuit includes: a first comparator that compares a voltage of the first data terminal and a first reference voltage; a second comparator that compares a voltage of the second data terminal and a second reference voltage; and a determination circuit that determines the kind of charger in accordance with output results of the first comparator and the second comparator.

2. The input-output circuit according to claim 1 , wherein the charger detection circuit detects the kind of pull-up/pull-down.

3. The input-output circuit according to claim 1 , wherein the charger detection circuit includes: a first pull-up circuit that is used for pulling up the first data terminal; a first pull-down circuit that is used for pulling down the first data terminal; a second pull-up circuit that is used for pulling up the second data terminal; and a second pull-down circuit that is used for pulling down the second data terminal, and the determination circuit connects the first data terminal to the first pull-up circuit and the second data terminal to the second pull-down circuit in a first step and connects the first data terminal to the first pull-down circuit and the second data terminal to the second pull-up circuit in a second step.

4. The input-output circuit according to claim 3 , further comprising: a control unit that receives a detection result from the charger detection circuit in response to the voltages of the first data terminal and the second data terminal, wherein the control unit notifies the charging circuit of the voltage detection.

5. The input-output circuit according to claim 4 , wherein the control unit notifies a main processor of the kind of charger connected to the connector, and the main processor instructs the charging circuit to perform a charging control according to the kind of charger.

6. The input-output circuit according to claim 4 , further including an identification terminal voltage detection circuit coupled to the control unit, the identification terminal voltage detection circuit configured to detect a voltage of an ID terminal and notify the control unit.

7. The input-output circuit according to claim 6 , further including a data line switching unit coupled to the control unit.

8. The input-output circuit according to claim 1 , wherein the charger detection circuit further includes a third comparator that compares the voltage of the second data terminal and a third reference voltage, and the determination circuit determines a determination result of the second data terminal as a middle level when the output of the second comparator is a low level and the output of the third comparator is a high level.

9. The input-output circuit according to claim 8 , further comprising: a control unit that receives a detection result from the charger detection circuit in response to the voltages of the first data terminal and the second data terminal, wherein the control unit notifies the charging circuit of the voltage detection.

10. The input-output circuit according to claim 9 , wherein the control unit notifies a main processor of the kind of charger connected to the connector, and the main processor instructs the charging circuit to perform a charging control according to the kind of charger.

11. The input-output circuit according to claim 10 , further including an identification terminal voltage detection circuit coupled to the control unit, the identification terminal voltage detection circuit configured to detect a voltage of an ID terminal and notify the control unit.

12. The input-output circuit according to claim 11 , further including a data line switching unit coupled to the control unit.

13. The input-output circuit according to claim 1 , further comprising: a control unit that receives a detection result from the charger detection circuit in response to the voltages of the first data terminal and the second data terminal, wherein the control unit notifies the charging circuit of the voltage detection.

14. The input-output circuit according to claim 13 , wherein the control unit notifies a main processor of the kind of charger connected to the connector, and the main processor instructs the charging circuit to perform a charging control according to the kind of charger.

15. The input-output circuit according to claim 13 , further including an identification terminal voltage detection circuit coupled to the control unit, the identification terminal voltage detection circuit configured to detect a voltage of an ID terminal and notify the control unit.

16. The input-output circuit according to claim 13 , further including a data line switching unit coupled to the control unit.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2012
From: WADA, ATSUSHI; MIZUKAMI, HAJIME; HATAKEYAMA, MITSUAKI; KOBAYASHI, SHIGETO
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 028395/0738 →
Priority Claims (1)
JP 2011-066491 · Mar 24, 2011 · national
Continuity (1)
Related Publication 20120256596A1 · Oct 11, 2012