Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device

1. A monolithic three dimensional memory device comprising:

a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate;

a plurality of control gate electrodes comprising at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located below the first device level and vertically spaced from the first control gate electrode by an air gap located substantially between the major surfaces of the first and second control gate electrodes; and

a charge storage region comprising metal silicide nanoparticles embedded in a charge storage dielectric matrix.

2. The monolithic three-dimensional memory device of claim 1 , further comprising a blocking dielectric layer located in contact with the plurality of control gate electrodes.

3. The monolithic three-dimensional memory device of claim 1 , wherein the charge storage region comprises a plurality of spaced apart charge storage segments.

4. The monolithic three-dimensional memory device of claim 3 , wherein the plurality of spaced apart charge storage segments comprise at least a first spaced apart charge storage segment located in the first device level and a second spaced apart charge storage segment located in the second device level.

5. The monolithic three-dimensional memory device of claim 1 , wherein the charge storage region comprises a continuous composite film.

6. The monolithic three-dimensional memory device of claim 1 , wherein the metal silicide nanoparticles comprise nickel silicide and the charge storage dielectric matrix comprises silicon nitride.

7. The monolithic three-dimensional memory device of claim 1 , wherein each of the plurality of control gate electrodes has a strip shape with major surfaces extending substantially parallel to the major surface of the substrate.

8. The monolithic three-dimensional memory device of claim 1 , further comprising a tunnel dielectric layer located between the charge storage region and the semiconductor channel.

9. The monolithic three-dimensional memory device of claim 1 , wherein the semiconductor channel has a pillar shape.

10. The monolithic three-dimensional memory device of claim 9 , wherein the entire pillar-shaped semiconductor channel extends substantially perpendicularly to the major surface of the substrate.

11. The monolithic three-dimensional memory device of claim 10 , further comprising one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from above, and another one of a source or drain electrode which contacts the pillar-shaped semiconductor channel from below.

12. The monolithic three-dimensional memory device of claim 1 , wherein:

the semiconductor channel has a U-shaped side cross section;

two wing portions of the U-shaped semiconductor channel extend substantially perpendicular to a major surface of the substrate are connected by a connecting portion which extends substantially parallel to the major surface of the substrate; and

an insulating fill is located over the connecting portion and separating two wing portions of the U-shaped semiconductor channel.

13. The monolithic three-dimensional memory device of claim 12 , further comprising one of a source or drain electrode which contacts the first wing portion of the semiconductor channel from above, another one of a source or drain electrode which contacts the second wing portion of the semiconductor channel from above, and a body contact electrode which contacts the connecting portion of the semiconductor channel from below.

14. The monolithic three-dimensional memory device of claim 1 , wherein:

at least a portion of the blocking dielectric layer has a clam shape which surrounds a respective control gate electrode; and

the charge storage dielectric matrix comprises a silicon nitride matrix.

15. The monolithic three-dimensional memory device of claim 1 , wherein the air gap is surrounded by an insulating layer which is located between the tunnel dielectric layer and the blocking dielectric layer.

16. The monolithic three-dimensional memory device of claim 1 , wherein the semiconductor channel, the plurality of control gate electrodes, and the charge storage region collectively constitute a vertically oriented NAND strings in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level, and wherein the substrate comprises a silicon substrate.

17. The monolithic three-dimensional memory device of claim 16 , further comprising an integrated circuit containing a driver circuit for the vertically oriented NAND strings located on the silicon substrate.

18. The monolithic three-dimensional memory device of claim 1 , wherein the charge storage region comprises a plurality of vertically spaced apart floating gates or a plurality of vertically spaced apart dielectric charge storage segments.

19. The monolithic three-dimensional memory device of claim 1 , wherein the air gap is surrounded by an insulating layer which is located between the tunnel dielectric layer and the blocking dielectric layer.

20. The monolithic three-dimensional memory device of claim 1 , wherein the metal silicide nanoparticles comprise a material selected from nickel silicide, cobalt silicide, tantalum silicide, tungsten silicide, molybdenum silicide, palladium silicide, platinum silicide, or an alloy thereof.