Integrated circuits having FinFETs with improved doped channel regions and methods for fabricating same

1. A method for fabricating an integrated circuit, the method comprising:

forming a channel region of a fin structure with a first side, a second side, an exposed first end surface and an exposed second end surface;

forming a gate overlying the first side and second side of the channel region;

forming an in-situ doped epitaxial layer along the exposed first end surface and the exposed second end surface;

annealing the integrated circuit to diffuse ions from the in-situ doped epitaxial layer into the channel region; and

forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region.

2. The method of claim 1 further comprising implanting ions into the channel region through the exposed first end surface and the exposed second end surface to form an implant region coextensive with the channel region.

3. The method of claim 1 wherein:

forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region comprises forming a source/drain in-situ doped epitaxial material overlying the in-situ doped epitaxial layer.

4. The method of claim 1 wherein forming a channel region of a fin structure comprises:

forming the fin structure comprising a first end region, a second end region, and the channel region between the first end region and the second end region; and

etching the first end region and the second end region to form the exposed first end surface and the exposed second end surface.

5. The method of claim 1 wherein forming a channel region of a fin structure comprises forming the channel region overlying a semiconductor substrate and having a fin height extending from the semiconductor substrate to an upper surface of the fin structure, and wherein the exposed first end surface and the exposed second end surface each extend from the semiconductor substrate to the upper surface of the fin structure.

6. The method of claim 1 wherein forming source/drain regions of the fin structure adjacent the exposed first end surface and the exposed second end surface of the channel region comprises epitaxially growing semiconductor material adjacent the exposed first end surface and the exposed second end surface.

7. The method of claim 1 wherein forming a channel region of a fin structure comprises forming the channel region of the fin structure overlying a semiconductor substrate surface with the exposed first end surface substantially perpendicular to the semiconductor substrate surface and the exposed second end surface substantially perpendicular to the semiconductor substrate surface.

8. A method for fabricating an integrated circuit, the method comprising:

forming a fin structure over a semiconductor material layer, wherein the fin structure has a fin height from the semiconductor material layer to an upper surface of the fin structure;

forming a gate structure overlying the fin structure, wherein a portion of the fin structure lying under the gate structure is defined as a channel region;

exposing end surfaces of the channel region, wherein each end surface of the channel region has an exposed height equal to the fin height;

implanting ions into the end surfaces of the channel region; and

forming source/drain regions of the fin structure adjacent the channel region.

9. The method of claim 8 wherein exposing end surfaces of the channel region comprises etching end regions of the fin structure to completely remove the end regions of the fin structure.

10. The method of claim 8 wherein exposing end surfaces of the channel region comprises etching end regions of the fin structure using the gate structure as a mask.

11. The method of claim 8 further comprising forming an epitaxial layer along the end surfaces after implanting ions into the end surfaces, wherein forming the source/drain regions comprises forming the source/drain regions on the epitaxial layer.

12. The method of claim 8 further comprising forming a first epitaxial layer along the exposed first end surface and the exposed second end surface, wherein forming source/drain regions of the fin structure adjacent the channel region comprises epitaxially growing semiconductor material adjacent the end surfaces and overlying the first epitaxial layer.

13. The method of claim 8 wherein implanting ions into the end surfaces of the channel region comprises:

forming an epitaxial layer along the end surfaces of the channel region; and

annealing the integrated circuit to diffuse ions from the epitaxial layer into the channel region.

14. The method of claim 8 wherein exposing end surfaces of the channel region comprises:

exposing opposite side surfaces and the upper surface of end regions of the fin structure; and

etching the end regions of the fin structure using the gate structure as a mask to expose end surfaces of the channel region.

15. The method of claim 8 wherein the channel region has a bottom surface coplanar with a top surface of the semiconductor material layer and wherein implanting ions into the end surfaces of the channel region comprises forming an implant region coextensive with the channel region.

16. A method for fabricating an integrated circuit, the method comprising:

forming a fin structure of semiconductor material, wherein the fin structure has opposite side surfaces and an upper surface extending therebetween;

forming a gate structure overlying a channel region of the fin structure;

exposing the opposite side surfaces and the upper surface of end regions of the fin structure;

etching the exposed opposite side surfaces and the upper surface of the end regions of the fin structure using the gate structure as a mask to form the channel region of semiconductor material with a first side adjacent the gate structure, an opposite second side adjacent the gate structure, an exposed first end surface aligned with the gate structure and an opposite exposed second end surface aligned with the gate structure; and

implanting ions into the exposed first end surface and the exposed second end surface of the channel region.

17. The method of claim 16 wherein the gate structure includes a spacer having a first side and a second side, wherein the exposed first end surface of the channel region is co-planar with the first side of the spacer, and wherein the exposed second end surface of the channel region is co-planar with the second side of the spacer.

18. The method of claim 16 further comprising:

forming an epitaxial layer along the first end surface and along the second end surface; and

forming source/drain regions over the epitaxial layer adjacent the first end surface and adjacent the second end surface.

19. The method of claim 16 wherein implanting ions into the exposed first end surface and the exposed second end surface of the channel region comprises:

forming an epitaxial layer along the exposed first end surface and the exposed second end surface of the channel region; and

annealing the integrated circuit to diffuse ions from the epitaxial layer into the channel region.

20. The method of claim 16 wherein:

forming the fin structure comprises forming the fin structure overlying a semiconductor material layer with a fin height from the semiconductor material layer to the upper surface; and

etching the end regions of the fin structure forms the exposed first end surface and the exposed second end surface with an exposed surface height equal to the fin height.