Multi-height FinFETs with coplanar topography
A semiconductor structure is provided that has semiconductor fins having variable heights without any undue topography. The semiconductor structure includes a semiconductor substrate having a first semiconductor surface and a second semiconductor surface, wherein the first semiconductor surface is vertically offset and located above the second semiconductor surface. An oxide region is located directly on the first semiconductor surface and/or the second semiconductor surface. A first set of first semiconductor fins having a first height is located above the first semiconductor surface of the semiconductor substrate. A second set of second semiconductor fins having a second height is located above the second semiconductor surface, wherein the second height is different than the first height and wherein each first semiconductor fin and each second semiconductor fin have topmost surfaces which are coplanar with each other.
1. A method of forming a semiconductor structure comprising:
providing a semiconductor substrate comprising a first semiconductor surface and a second semiconductor surface, wherein said first semiconductor surface is vertically offset and located above said second semiconductor surface, and wherein a pair of spaced apart semiconductor mandrel structures is present on a portion of said first semiconductor surface of the semiconductor substrate;
forming an oxide region on at least one of said first semiconductor surface and the second semiconductor surface;
forming a first set of first semiconductor fins having a first height from one sidewall surface of each semiconductor mandrel structure and located above said first semiconductor surface, and forming a second set of second semiconductor fins having a second height from another sidewall surface of each semiconductor mandrel structure and located above the second semiconductor surface, wherein said second height is different than the first height, and wherein said first semiconductor fin and said second semiconductor fin each have a topmost surface and wherein said topmost surface of the first semiconductor fin is coplanar with the topmost surface of the second semiconductor fin; and
removing each semiconductor mandrel structure from atop portions of the first semiconductor surface.
2. The method of claim 1 , further comprising forming an insulator layer on portions of the first semiconductor surface previously occupied by each semiconductor mandrel structure.
3. The method of claim 1 , further comprising forming a gate structure straddling each of the first and second semiconductor fins.
4. The method of claim 1 , wherein said providing the semiconductor structure comprises:
providing a layer of hard mask material on a surface of a bulk semiconductor substrate;
forming at least one opening through the layer of hard mask material and into a portion of the bulk semiconductor substrate to provide said first semiconductor surface;
epitaxially growing each semiconductor mandrel structure on each vertical sidewall surface of the bulk semiconductor substrate and within said at least one opening, wherein a gap remains between each semiconductor mandrel structure formed in each opening;
filling each opening and gap with a dielectric material;
removing remaining portions of the layer of hard mask material to expose portions of the semiconductor substrate;
recessing the exposed portions of the semiconductor structure to provide said second semiconductor surface; and
removing said dielectric material.
5. The method of claim 1 , wherein said forming the first set of semiconductor fins and said forming the second set of semiconductor fins comprises an epitaxial growth process.
6. The method of claim 1 , wherein said removing each semiconductor mandrel structure comprises a selective etch process.
7. The method of claim 1 , wherein said oxide regions is formed only on the first semiconductor surface.
8. The method of claim 1 , wherein the oxide regions are formed only on the second semiconductor surface.
9. The method of claim 1 , wherein the oxide region is formed on both the first semiconductor surface and the second semiconductor surface.