Shallow trench isolation integration methods and devices formed thereby
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.
1. A method for forming a semiconductor device, comprising:
etching a set of trenches in a substrate;
forming a first liner layer over the set of trenches;
forming a second liner layer over the first liner layer;
filling the set of trenches over the second liner layer with a first fill material;
polishing and etching back the first fill material to leave a portion of the first fill material remaining;
removing the second liner layer disposed above the remaining portion of the first fill material to leave a portion of the second liner layer remaining and a portion of the first liner layer remaining disposed above the remaining portion of the first fill material;
depositing a silicon layer after the second liner layer has been removed; and
refilling the set of trenches with a second fill material, the second fill material being in contact with a portion of the first liner layer, overlying and/or in contact with the remaining portion of the second liner layer, and overlying and/or in contact with the remaining portion of the first fill material.
2. The method of claim 1 , further comprising:
polishing the second fill material; and
etching back the second fill material.
3. The method of claim 1 , the first liner layer comprising an in-situ steam generation (ISSG)-based layer.
4. The method of claim 1 , the second liner layer being selected from a group consisting of: silicon nitride (SiN) and poly-silicon.
5. The method of claim 1 , the filling comprising filling the set of trenches being filled via an enhanced high aspect ratio process (eHARP).
6. The method of claim 1 , the refilling comprising refilling the set of trenches with a high density plasma (HDP).
7. The method of claim 1 , further comprising a device formed according to the method of claim 1 .
8. The method of claim 7 , wherein the step of depositing the silicon layer is replaced by removing the second liner layer with a direct thermal treatment process.
9. A method for forming a semiconductor device, comprising:
etching a set of trenches in a substrate;
forming a first liner layer over the set of trenches;
forming a second liner layer over the first liner layer;
filling the set of trenches over the second liner layer via an enhanced high aspect ratio process (eHARP);
polishing and etching the semiconductor device after the filling;
removing the second liner layer, leaving a portion of the first liner layer disposed above the remaining portion of material filled by eHARP;
depositing a silicon layer; and
filling the set of trenches with a high density plasma (HDP) in such a way that the HDP is substantially fully surrounded at three sides thereof by the silicon layer.
10. The method of claim 9 , further comprising:
polishing the HDP; and
etching back the HDP.
11. The method of claim 9 , further comprising depositing the silicon layer after the second liner layer has been removed.
12. The method of claim 9 , the first liner layer comprising an in-situ steam generation (ISSG)-based layer.
13. The method of claim 9 , the second liner layer being selected from a group consisting of: silicon nitride (SiN) and poly-silicon.
14. The method of claim 9 , the second liner layer being removed with at least one of the following: a hot phosphorous process, or a direct thermal treatment process.
15. The method of claim 9 , further comprising a device formed according to the method of claim 9 .
16. A method for forming a semiconductor device, comprising:
etching a set of trenches in a substrate;
forming a shallow trench isolation (STI) layer, the STI layer comprising a first liner layer and a second liner layer;
filling the set of trenches over the second liner layer via an enhanced high aspect ratio process (eHARP);
polishing and etching the semiconductor device after the filling;
removing the second liner layer, leaving a portion of the first liner layer disposed above the remaining portion of material filled by eHARP;
depositing a silicon layer;
filling the set of trenches with a high density plasma (HDP) in such a way that the HDP is substantially fully surrounded at three sides thereof by the silicon layer;
polishing the HDP; and
etching back the HDP.
17. The method of claim 16 , further comprising depositing the silicon layer after the second liner layer has been removed.
18. The method of claim 16 , the first liner layer comprising an in-situ steam generation (ISSG)-based layer, and the second liner layer being selected from a group consisting of: silicon nitride (SiN) and poly-silicon.
19. A device formed according to the method of claim 16 .