Integrated circuits and methods for fabricating integrated circuits with silicide contacts on non-planar structures
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate and forming fins over the semiconductor substrate. Each fin is formed with sidewalls. The method further includes conformally depositing a metal film stack on the sidewalls of each fin. In the method, the metal film stack is annealed to form a metal silicide film over the sidewalls of each fin.
1. A method for fabricating an integrated circuit comprising:
providing a semiconductor substrate;
forming fins over the semiconductor substrate, wherein each fin is formed from semiconductor material, and wherein the semiconductor material of each fin has sidewalls;
forming a silicon layer on the sidewalls of each fin;
conformally depositing a metal film on the sidewalls of the semiconductor material of each fin; and
annealing the metal film to form a metal silicide film on the sidewalls of the semiconductor material of each fin, wherein formation of the metal silicide film consumes all of the silicon layer.
2. The method of claim 1 wherein forming fins comprises defining a gap between adjacent fins, and wherein conformally depositing a metal film stack does not fill the gap.
3. The method of claim 1 further comprising pre-cleaning the fins with a fluorine-containing chemistry before conformally depositing the metal film stack.
4. The method of claim 1 further comprising stripping non-reacted portions of the metal film stack after annealing.
5. The method of claim 1 wherein forming the silicon layer over the sidewalls of each fin comprises forming the silicon layer over the sidewalls of each fin before conformally depositing a metal film stack over the sidewalls of each fin.
6. The method of claim 5 wherein forming the silicon layer over the sidewalls of each fin comprises selectively growing epitaxial silicon on the sidewalls of each fin before conformally depositing the metal film stack, wherein the metal film stack is conformally deposited directly onto the silicon layer.
7. The method of claim 5 wherein forming the silicon layer over the sidewalls of each fin comprises depositing silicon on the sidewalls of each fin before conformally depositing the metal film stack, wherein the metal film stack is conformally deposited directly onto the silicon layer.
8. The method of claim 5 wherein forming the silicon layer over the sidewalls of each fin comprises exposing the sidewalls of each fin to a silicon source selected from Si2H6, Si3H8, and SiH4.
9. The method of claim 1 wherein forming a silicon layer over the sidewalls of each fin comprises forming a silicon layer having a thickness of less than about 1 nm.
10. A method for fabricating an integrated circuit comprising:
providing a semiconductor substrate;
forming fins over the semiconductor substrate, wherein each fin has sidewalls;
conformally depositing a metal film stack over the sidewalls of each fin by conformally depositing at least two layers of metal over the sidewalls of each fin; and
annealing the metal film stack to form a metal silicide film over the sidewalls of each fin.
11. The method 10 wherein conformally depositing a metal film stack over the sidewalls of each fin comprises depositing at least two layers of metal by atomic layer deposition (ALD).
12. The method of claim 11 wherein conformally depositing a metal film stack over the sidewalls of each fin comprises:
depositing a first layer of platinum over the sidewalls of each fin by ALD; and
depositing a layer of nickel over the first layer of platinum by ALD.
13. The method of claim 12 wherein conformally depositing a metal film stack over the sidewalls of each fin further comprises depositing a second layer of platinum over the layer of nickel by ALD.
14. The method of claim 12 wherein depositing the first layer of platinum over the sidewalls of each fin by ALD comprises exposing the sidewalls of each fin to a platinum precursor selected from Pt(PF3)4, MeCpTtMe3, CpPtMe3, Pt(acac)2, and wherein depositing the layer of nickel over the first layer of platinum by ALD comprises exposing the first layer of platinum to a nickel precursor selected from Ni(PF3)4, Ni(iPr-MeAMD)2, Ni(tBu-MeAMD)2, Bis(dimethylamimp-methyl-butoxy)Ni, Ni(MeCp)2, and bis-(2-Imino-Pen-En 4-Trifluoro-Acetylacetonato) Ni(II)-Mi(ktfaa)2.
15. A method for fabricating an integrated circuit comprising:
forming a non-planar structure of semiconductor material having a bottom surface over an upper surface of an insulator layer, wherein the non-planar structure of semiconductor material includes sidewalls;
depositing a metal silicide material over sidewalls of the non-planar structure and on the insulator layer; and
annealing the metal silicide material to form a metal silicide film from the metal silicide material and from the sidewalls of the non-planar structure, wherein the metal silicide film contacts the insulator layer.
16. The method of claim 15 further comprising forming a silicon layer over the sidewalls of the non-planar structure, wherein annealing the metal silicide material comprises consuming all of the silicon layer.
17. The method of claim 15 wherein depositing the metal silicide material comprises depositing at least two layers of metal over the sidewalls of the non-planar structure.