Balancing asymmetric spacers
An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs.
1. A method of forming an integrated circuit, comprising:
forming at least a first FET comprising a first gate structure and a first spacer structure formed on the sidewall of said first gate structure;
forming at least a second FET comprising a second gate structure and a second spacer structure formed on the sidewall of said second gate structure, a semiconductor alloy being embedded in the source and/or drain regions of said second FET;
forming a mask layer on said integrated circuit so as to cover said second FET and leave said first FET exposed;
performing an ion implantation in the presence of said mask layer; and
after performing said ion implantation, performing an etching process in the presence of said mask layer so as to decrease the thickness of said first spacer structure.
2. The method of claim 1 , wherein said first FET and said second FET have opposite polarities.
3. The method of claim 1 , wherein said first FET is an N-channel FET and said second FET is a P-channel FET.
4. The method of claim 1 , wherein said mask layer comprises a photoresist.
5. The method of claim 1 , further comprising removing said mask layer after performing said etching process.
6. The method of claim 1 , wherein said integrated circuit is formed partly in and partly on a semiconductor layer.
7. The method of claim 1 , wherein said embedded semiconductor alloy comprises a portion extending above the surface of said semiconductor layer.
8. The method of claim 1 , wherein said portion of said embedded semiconductor alloy protrudes by 10 nm or more from said surface of said semiconductor layer.
9. The method of claim 1 , wherein said embedded semiconductor alloy comprises SiGe.
10. The method of claim 1 , wherein a concentration of Ge varies within said embedded semiconductor alloy.
11. The method of claim 1 , wherein said etching process comprises a dry etching process.
12. The method of claim 1 , wherein said etching process does not affect said second FET.
13. The method of claim 1 , further comprising:
forming an inner portion of said first spacer structure and an inner portion of said second spacer structure next to said first gate structure and said second gate structure, respectively; and
forming an outer portion of said first spacer structure and an outer portion of said second spacer structure above said inner portion of said first spacer structure and said inner portion of said second spacer structure, respectively.
14. The method of claim 13 , wherein said mask layer is formed after forming said outer portion of said first spacer structure and said outer portion of said second spacer structure.
15. The method of claim 13 , further comprising performing at least one ion implantation after forming said inner portions of said first spacer structure and said second spacer structure and before forming said outer portions of said first spacer structure and said second spacer structure.
16. The method of claim 1 , wherein said first gate structure and said second gate structure are formed according to the HKMG technology.
17. The method of claim 1 , wherein at least one of said first gate structure and said second gate structure comprises SiON and polysilicon.
18. A method of forming an integrated circuit, comprising:
forming at least a first FET comprising a first gate structure and a first spacer structure formed on the sidewall of said first gate structure;
forming at least a second FET comprising a second gate structure and a second spacer structure formed on the sidewall of said second gate structure, a semiconductor alloy being embedded in the source and/or drain regions of said second FET;
forming a mask layer on said integrated circuit so as to cover said second FET and leave said first FET exposed;
performing an etching process in the presence of said mask layer so as to decrease the thickness of said first spacer structure;
removing said mask layer after performing said etching process; and
performing a silicidation process after removing said mask layer so as to form a metal silicide layer on predetermined surface portions of said integrated circuit.
19. The method of claim 18 , further comprising:
forming an inner portion of said first spacer structure and an inner portion of said second spacer structure next to said first gate structure and said second gate structure, respectively; and
forming an outer portion of said first spacer structure and an outer portion of said second spacer structure above said inner portion of said first spacer structure and said inner portion of said second spacer structure, respectively.
20. The method of claim 19 , further comprising performing at least one ion implantation after forming said inner portions of said first spacer structure and said second spacer structure and before forming said outer portions of said first spacer structure and said second spacer structure.
21. A method of forming an integrated circuit, comprising:
forming at least a first FET comprising a first gate structure and a first spacer structure formed on the sidewall of said first gate structure;
forming at least a second FET comprising a second gate structure and a second spacer structure formed on the sidewall of said second gate structure, a semiconductor alloy being embedded in the source and/or drain regions of said second FET;
forming a mask layer on said integrated circuit so as to cover said second FET and leave said first FET exposed;
performing an ion implantation in the presence of said mask layer;
after performing said ion implantation, performing an etching process in the presence of said mask layer so as to decrease the thickness of said first spacer structure;
removing said mask layer after performing said etching process; and
performing a silicidation process after removing said mask layer so as to form a metal silicide layer on predetermined surface portions of said integrated circuit.