Fin field effect transistor with dielectric isolation and anchored stressor elements
A first fin field effect transistor and a second fin field effect transistor are formed on an insulator layer overlying a semiconductor material layer. A first pair of trenches is formed through the insulator layer in regions in which a source region and a drain region of the first fin field effect transistor is to be formed. A second pair of trenches is formed partly into the insulator layer without extending to the top surface of the semiconductor material layer. The source region and the drain region of the first field effect transistor can be epitaxial stressor material portions that are anchored to, and epitaxially aligned to, the semiconductor material layer and apply stress to the channel of the first field effect transistor to enhance performance. The insulator layer provides electrical isolation from the semiconductor material layer to the second field effect transistor.
1. A semiconductor structure comprising:
a doped semiconductor layer located in a semiconductor substrate;
an insulator layer located on a top surface of said doped semiconductor layer;
a first semiconductor fin located on a first portion of a top surface of said insulator layer;
a first gate stack straddling said first semiconductor fin;
a first source region contacting a first end wall of said first semiconductor fin and said doped semiconductor layer and extending through said insulator layer;
a first drain region contacting a second end wall of said first semiconductor fin and said doped semiconductor layer, spaced from said first source region, and extending through said insulator layer;
a second semiconductor fin located on a second portion of said top surface of said insulator layer;
a second gate stack straddling said second semiconductor fin;
a second source region contacting a first end wall of said second semiconductor fin and vertically spaced from said semiconductor substrate by said insulator layer; and
a second drain region contacting a second end wall of said second semiconductor fin and vertically spaced from said semiconductor substrate by said insulator layer.
2. The semiconductor structure of claim 1 , wherein said doped semiconductor layer is single crystalline, and each of said first source region and said first drain region includes a single crystalline semiconductor material portion that is epitaxially aligned to said doped semiconductor layer.
3. The semiconductor structure of claim 1 , wherein said doped semiconductor layer is single crystalline, and said first source region and said first drain region includes a single crystalline semiconductor material having a lattice constant that is different from a lattice constant of a single crystalline semiconductor material in said doped semiconductor layer.
4. The semiconductor structure of claim 3 , wherein said first source region and said second source region applies a compressive stress or a tensile stress to said first semiconductor fin.
5. The semiconductor structure of claim 3 , wherein said first semiconductor fin comprises silicon, and said single crystalline semiconductor material of said first source region and said first drain region comprises a p-doped silicon-germanium alloy material.
6. The semiconductor structure of claim 1 , wherein said first semiconductor fin is single crystalline, and each of said first source region and said first drain region includes a single crystalline semiconductor material portion that is epitaxially aligned to said first semiconductor fin.
7. The semiconductor structure of claim 6 , wherein said doped semiconductor layer is single crystalline, and each of said first source region and said first drain region includes another single crystalline semiconductor material portion that is epitaxially aligned to a single crystalline semiconductor material of said doped semiconductor layer.
8. The semiconductor structure of claim 7 , wherein said single crystalline semiconductor material portion and said another single crystalline semiconductor material portion contact each other at a grain boundary that extends to a vertical sidewall of said insulator layer.
9. The semiconductor structure of claim 1 , wherein each of said second source region and said second drain region contacts a portion of a topmost surface of said insulator layer.
10. The semiconductor structure of claim 1 , wherein said second source region and said second drain region contact recessed surfaces of said insulator layer.
11. A method of forming a semiconductor structure comprising:
forming a first semiconductor fin and a second semiconductor fin on a top surface of a stack, from bottom to top, of a semiconductor substrate and an insulator layer, wherein said forming said first semiconductor fin and said second semiconductor fin comprises lithographically patterning a topmost semiconductor material layer of a semiconductor-on-insulator substrate;
forming a first gate stack and a second gate stack straddling said first semiconductor fin and said second semiconductor fin, respectively;
forming a first trench and a second trench through said insulator layer and into an upper portion of said semiconductor substrate by etching unmasked portions of said first semiconductor fin and said insulator layer employing a combination of at least a patterned mask layer and said first gate stack as an etch mask, wherein said first trench is formed on one side of said first gate stack and said second trench is formed on another side of said gate stack;
forming a first source region in said first trench, on a first end wall of a remaining portion of said first semiconductor fin, and on a first portion of said semiconductor substrate, and a first drain region in said second trench, on a second end wall of said remaining portion of said semiconductor fin, and on a second portion of said semiconductor substrate; and
forming a second source region and a second drain region on a remaining portion of said second semiconductor fin, wherein said second source region and said second drain region are vertically spaced from said semiconductor substrate by said insulator layer.
12. The method of claim 11 , further comprising forming a doped semiconductor layer within said semiconductor substrate, wherein said first trench and said second trench are formed into said doped semiconductor material layer.
13. The method of claim 12 , wherein said doped semiconductor layer is single crystalline, and each of said first source region and said first drain region includes a single crystalline semiconductor material portion that is formed with epitaxial alignment to said doped semiconductor layer.
14. The method of claim 12 , wherein said doped semiconductor layer is single crystalline, and said first source region and said first drain region include a single crystalline semiconductor material having a lattice constant that is different from a lattice constant of a single crystalline semiconductor material in said doped semiconductor layer.
15. The method of claim 12 , wherein said doped semiconductor layer has a doping of a first conductivity type, said first source region and said second source region have a doping of a second conductivity type, and said second conductivity type is the opposite of said first conductivity type.
16. The method of claim 11 , wherein each of said first source region and said first drain region is formed by a selective epitaxy process that simultaneously grows a semiconductor material from physically exposed surfaces of said semiconductor substrate within said first trench and said second trench and from physically exposed surfaces of said remaining portion of said first semiconductor fin.
17. The method of claim 16 , wherein a grain boundary between single crystalline semiconductor material portions is formed within each of said first source region and said first drain region.
18. The method of claim 11 , further comprising forming a gate spacer around said first gate stack, wherein said combination further includes said gate spacer.
19. The method of claim 18 , wherein a sidewall of said first trench is vertically coincident with a first outer sidewall of said gate spacer and with a first end wall of a remaining portion of said first semiconductor fin, and a sidewall of said second trench is vertically coincident with a second outer sidewall of said gate spacer and with a second end wall of said remaining portion of said first semiconductor fin.
20. The method of claim 18 , wherein said gate spacer is formed by:
depositing a conformal dielectric material layer on said first gate stack, said second gate stack, said first semiconductor fin, and said second semiconductor fin; and
anisotropically etching a portion of said conformal dielectric material layer located on said first semiconductor fin and said first gate stack.