Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.
1. An electrical junction comprising a metal oxide interface layer disposed between a contact metal and a group IV semiconductor, the semiconductor comprising a source or drain of a transistor, the interface layer configured to reduce a height of a Schottky barrier between the contact metal and the semiconductor from that which would exist at a contact junction between the contact metal and the semiconductor without the interface layer disposed therebetween, and wherein the interface layer has a thickness of approximately 0.1 nm to 5 nm.
2. The electrical junction of claim 1 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.
3. The electrical junction of claim 1 , wherein the contact metal is a metal or a stack of metals deposited on the interface layer.
4. The electrical junction of claim 3 , wherein the interface layer comprises TiO 2 .
5. The electrical junction of claim 1 , wherein the interface layer has a thickness of approximately less than 1 nm.
6. The electrical junction of claim 5 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.
7. The electrical junction of claim 5 , wherein the contact metal is a metal or a stack of metals deposited on the interface layer.
8. The electrical junction of claim 7 , wherein the interface layer comprises TiO 2 .
9. The electrical junction of claim 1 , wherein the interface layer has a thickness of approximately less than 0.5 nm.
10. The electrical junction of claim 9 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.
11. The electrical junction of claim 9 , wherein the contact metal is a metal or a stack of metals deposited on the interface layer.
12. The electrical junction of claim 11 , wherein the interface layer comprises TiO 2 .
13. The electrical junction of claim 1 , wherein the interface layer has a thickness of approximately less than 0.2 nm.
14. The electrical junction of claim 13 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.
15. The electrical junction of claim 13 , wherein the contact metal is a metal or a stack of metals deposited on the interface layer.
16. The electrical junction of claim 15 , wherein the interface layer comprises TiO 2 .
17. The electrical junction of claim 1 , wherein the contact metal does not form a silicide.
18. The electrical junction of claim 1 , wherein the contact metal does not react with the group IV semiconductor.
19. An electrical junction comprising a metal oxide barrier layer disposed between a contact metal and a group IV semiconductor, the semiconductor comprising a source or drain of a transistor, the barrier layer configured to reduce a height of a Schottky barrier between the contact metal and the semiconductor from that which would exist at a contact junction between the contact metal and the semiconductor without the barrier layer disposed therebetween, said Schottky barrier being less than that which would exist if a silicide of the contact metal were used as the barrier layer instead of the metal oxide interface layer.
20. The electrical junction of claim 19 , wherein the barrier layer has a thickness less than that which would exist if the silicide of the contact metal were used as the barrier layer instead of the metal oxide interface layer.
21. An electrical junction, comprising a conductor; a semiconductor selected from a list consisting of Si, Ge, C (a crystal structure of which is selected from a list comprising a diamond lattice, a fulleride or a polymer), an alloy of Ge and Si, an alloy of Ge and C, an alloy of Si and C, and an alloy of Si, Ge, and C; and an interface layer disposed therebetween, the semiconductor comprising a source or drain of a transistor, and the interface layer comprising a metal oxide and having a thickness of approximately 0.1 nm to 5 nm.
22. The electrical junction of claim 21 , wherein the semiconductor comprises an n-type doped source or drain of a transistor.
23. The electrical junction of claim 21 , wherein the contact metal is a metal or a stack of metals deposited on the interface layer.
24. The electrical junction of claim 23 , wherein the semiconductor comprises an n-type doped group IV semiconductor.
25. The electrical junction of claim 24 , wherein the interface layer comprises TiO 2 .
26. The electrical junction of claim 23 , wherein the interface layer comprises TiO 2 .
27. The electrical junction of claim 22 , wherein the interface layer comprises TiO 2 .
28. The electrical junction of claim 21 , wherein the interface layer comprises TiO 2 .
29. The electrical junction of claim 28 , wherein the interface layer has a thickness of approximately less than 1 nm.
30. The electrical junction of claim 28 , wherein the interface layer has a thickness of approximately less than 0.5 nm.