Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region
Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance C cb and collector resistance R c are both minimized.
1. A bipolar semiconductor device comprising:
a first terminal region in a semiconductor substrate;
a second terminal region in a first semiconductor layer on said semiconductor substrate, said second terminal region being aligned above said first terminal region;
a third terminal region in a second semiconductor layer on said first semiconductor layer, said third terminal region being aligned above said second terminal region;
an opening extending vertically through said first semiconductor layer and positioned laterally adjacent to said second terminal region;
a trench in said semiconductor substrate aligned below said opening, said trench being wider than said opening and having a relatively high aspect ratio with a depth of said trench being less than a width of said trench;
at least one isolation material filling said trench so as to form a trench isolation region, said at least one isolation material also filling said opening; and
a doped region in said semiconductor substrate aligned below and immediately adjacent to a bottom surface of said trench.
2. The bipolar semiconductor device of claim 1 , said trench having a center portion extending a first depth into said semiconductor substrate and edges portions extending a second depth into said semiconductor substrate, said second depth being greater than said first depth.
3. The bipolar semiconductor device of claim 1 , said semiconductor substrate and said second semiconductor layer comprising a first semiconductor material and said first semiconductor layer comprising a second semiconductor material different from said first semiconductor material.
4. The bipolar semiconductor device of claim 3 , said first semiconductor material comprising silicon and said second semiconductor material comprising silicon germanium.
5. The bipolar semiconductor device of claim 1 , said doped region being doped with a dopant comprising any of germanium, boron, arsenic, argon, neon, and silicon.
6. The bipolar semiconductor device of claim 1 , said opening laterally surrounding said second terminal region.
7. The bipolar semiconductor device of claim 1 , said trench defining a pedestal of said first terminal region at a top surface of said semiconductor substrate adjacent to said second terminal region.
8. A bipolar semiconductor device comprising:
a first terminal region in a semiconductor substrate;
a second terminal region in a first semiconductor layer on said semiconductor substrate, said second terminal region being aligned above said first terminal region;
a third terminal region in a second semiconductor layer on said first semiconductor layer, said third terminal region being aligned above said second terminal region;
an opening extending vertically through said first semiconductor layer and positioned laterally adjacent to said second terminal region;
a trench in said semiconductor substrate aligned below said opening, said trench being wider than said opening and having a relatively high aspect ratio with a depth of said trench being less than a width of said trench, said trench having edge portions and a center portion between said edge portions;
at least one isolation material filling said trench so as to form a trench isolation region, said at least one isolation material also filling said opening; and
a doped region in said semiconductor substrate aligned below and immediately adjacent to a bottom surface of said trench at said center portion only such that said edge portions extend laterally beyond said doped region.
9. The bipolar semiconductor device of claim 8 , said center portion of said trench extending a first depth into said semiconductor substrate and said edges portions extending a second depth into said semiconductor substrate, said second depth being greater than said first depth.
10. The bipolar semiconductor device of claim 8 , said semiconductor substrate and said second semiconductor layer comprising a first semiconductor material and said first semiconductor layer comprising a second semiconductor material different from said first semiconductor material.
11. The bipolar semiconductor device of claim 10 , said first semiconductor material comprising silicon and said second semiconductor material comprising silicon germanium.
12. The bipolar semiconductor device of claim 8 , said doped region being doped with a dopant comprising any of germanium, boron, arsenic, argon, neon, and silicon.
13. The bipolar semiconductor device of claim 8 , said opening laterally surrounding said second terminal region and said trench defining a pedestal of said first terminal region at a top surface of said semiconductor substrate adjacent to said second terminal region.
14. A bipolar semiconductor device comprising:
a first terminal region in a semiconductor substrate, said semiconductor substrate comprising a first semiconductor material;
a second terminal region in a first semiconductor layer on said semiconductor substrate, said first semiconductor layer comprising a second semiconductor material different from said first semiconductor material and said second terminal region being aligned above said first terminal region;
a third terminal region in a second semiconductor layer on said first semiconductor layer, said third terminal region being aligned above said second terminal region;
an opening extending vertically through said first semiconductor layer and positioned laterally adjacent to said second terminal region;
a trench in said semiconductor substrate aligned below said opening, said trench being wider than said opening and having a relatively high aspect ratio with a depth of said trench being less than a width of said trench, said trench having edge portions and a center portion between said edge portions;
at least one isolation material filling said trench so as to form a trench isolation region, said at least one isolation material also filling said opening; and
a doped region in said semiconductor substrate aligned below and immediately adjacent to a bottom surface of said trench at said center portion only such that said edge portions extend laterally beyond said doped region.
15. The bipolar semiconductor device of claim 14 , said center portion of said trench extending a first depth into said semiconductor substrate and said edges portions extending a second depth into said semiconductor substrate, said second depth being greater than said first depth.
16. The bipolar semiconductor device of claim 14 , said first semiconductor material comprising silicon and said second semiconductor material comprising silicon germanium.
17. The bipolar semiconductor device of claim 14 , said second semiconductor layer comprising silicon.
18. The bipolar semiconductor device of claim 14 , said doped region being doped with a dopant comprising any of germanium, boron, arsenic, argon, neon, and silicon.
19. The bipolar semiconductor device of claim 14 , said opening laterally surrounding said second terminal region.
20. The bipolar semiconductor device of claim 14 , said trench defining a pedestal of said first terminal region at a top surface of said semiconductor substrate adjacent to said second terminal region.