Methods of forming replacement gate structures for transistors and the resulting devices
Disclosed herein are illustrative methods and devices that involve forming spacers with internally trimmed internal surfaces to increase the width of the upper portions of a gate cavity. In some embodiments, the internal surface of the spacer has a stepped cross-sectional configuration or a tapered cross-sectional configuration. In one example, a device is disclosed wherein the P-type work function metal for a PMOS device is positioned only within the lateral space defined by the untrimmed internal surfaces of the spacers, while the work function adjusting metal for the NMOS device is positioned laterally between the lateral spaces defined by both the trimmed and untrimmed internal surfaces of the sidewall spacers.
1. A method, comprising:
performing at least one first etching process to remove a sacrificial gate structure for a transistor to thereby define a gate cavity defined by internal surfaces of spaced-apart sidewall spacers, said gate cavity having an opening having a first width;
depositing at least one material layer in said gate cavity;
forming a recessed sacrificial material layer in said gate cavity above said at least one material layer;
performing at least one second etching process to remove said at least one material layer within said gate cavity above said recessed sacrificial material layer so as to thereby expose a portion of said internal surfaces of said spaced-apart sidewall spacers positioned above said recessed sacrificial material layer;
performing a spacer trimming etch process on said exposed portions of said internal surfaces of said spaced-apart sidewall spacers to reduce a thickness of at least a portion of said sidewall spacers in the presence of said recessed sacrificial material layer and thereby increase a size of said opening to a second width that is greater than said first width; and
removing said recessed sacrificial material layer from said gate cavity.
2. The method of claim 1 , wherein, after performing said spacer trimming etch process, said internal surfaces of said spaced-apart sidewall spacers have a stepped cross-sectional configuration.
3. The method of claim 1 , wherein said internal surfaces of said spaced-apart spacers that were subjected to said spacer trimming etch process are outwardly tapered surfaces.
4. The method of claim 1 , wherein said spacer trimming etch process is one of an anisotropic etching process or an isotropic etching process.
5. The method of claim 1 , wherein said transistor is one of an NMOS transistor or a PMOS transistor.
6. The method of claim 1 , further comprising, after removing said recessed sacrificial material layer from said gate cavity, forming additional layers of material in said gate cavity having said opening with said second width.
7. The method of claim 1 , wherein forming said recessed sacrificial material layer comprises:
over-filling said gate cavity with said sacrificial material; and
performing a recess etch process on said sacrificial material.
8. A method, comprising:
forming sidewall spacers adjacent a sacrificial gate structure;
performing at least first one etching process to remove said sacrificial gate structure for said transistor to thereby define a gate cavity defined by internal surfaces of said sidewall spacers, said gate cavity having an opening having a first width;
depositing a gate insulation layer in said gate cavity and on said internal surfaces of said sidewall spacers;
depositing a first metal layer on said gate insulation layer in said gate cavity;
forming a recessed sacrificial material layer in said gate cavity above said first metal layer;
performing at least one second etching process to remove said gate insulation layer and said first metal layer positioned within said gate cavity above said recessed sacrificial material layer so as to thereby expose a portion of said internal surfaces of said sidewall spacers; and
performing a spacer trimming etch process on said exposed portions of said internal surfaces of said sidewall spacers to reduce a thickness of at least a portion of said sidewall spacers and to increase a size of said opening to a second width that is greater than said first width.
9. The method of claim 8 , wherein, after performing said spacer trimming etch process, said internal surfaces of said sidewall spacers have a stepped cross-sectional configuration.
10. The method of claim 8 , wherein said internal surfaces of said sidewall spacers that were subjected to said spacer trimming etch process are outwardly tapered surfaces.
11. The method of claim 8 , wherein said spacer trimming etch process is one of an anisotropic etching process or an isotropic etching process.
12. The method of claim 8 , wherein, after performing said spacer trimming etch process, the method further comprises:
removing said sacrificial material layer; and
forming additional layers of metal in said gate cavity having said opening with said second width.
13. The method of claim 8 , wherein, after performing said spacer trimming etch process, the method further comprises:
removing said sacrificial material layer;
removing said first metal layer from within said gate cavity so as to expose said gate insulation layer;
forming a second metal layer on said gate insulation layer; and
forming additional layers of metal in said gate cavity above said second metal layer.
14. The method of claim 8 , wherein, after performing said spacer trimming etch process, the method further comprises:
removing said sacrificial material layer so as to expose said first metal layer;
forming a second metal layer on said first metal layer; and
forming additional layers of metal in said gate cavity above said second metal layer.
15. A method, comprising:
forming a sacrificial gate structure above an active area of a semiconductor device;
forming a sidewall spacer structure adjacent sidewalls of said sacrificial gate structure;
performing at least one first etching process to remove said sacrificial gate structure selectively to said sidewall spacer structure so as to form a gate cavity defined by internal surfaces of said sidewall spacer structure, an upper portion of said gate cavity having a first opening width;
depositing at least one material layer in said gate cavity;
depositing a sacrificial material above said at least one material layer, said sacrificial material overfilling said gate cavity;
performing a second etching process to remove an excess portion of said sacrificial material overfilling said gate cavity and to recess an upper surface of said sacrificial material within said gate cavity selectively to said at least one material layer, said recessed sacrificial material exposing an upper sidewall portion of said at least one material layer;
performing at least one third etching process to remove said upper sidewall portion of said at least one material layer within said gate cavity selectively to said recessed sacrificial material and said sidewall spacer structure and to expose said internal surfaces of an upper sidewall portion of said sidewall spacer structure above said recessed sacrificial material; and
performing a spacer trimming etch process on said upper sidewall portion of said sidewall spacer structure so as to reduce a thickness of at least a portion of said upper sidewall portion of said sidewall spacer structure and to increase a size of said upper portion of said gate cavity from said first opening width to a second opening width.
16. The method of claim 15 , wherein, after performing said spacer trimming etch process, said internal surfaces of said sidewall spacer structure have a stepped cross-sectional configuration.
17. The method of claim 15 , wherein, after performing said spacer trimming etch process, at least a portion of said upper sidewall portion of said sidewall spacer structure above said recessed sacrificial material has outwardly tapered internal surfaces.
18. The method of claim 15 , wherein reducing said thickness of said at least said portion of said upper sidewall portion of said sidewall spacer structure comprises removing a first thickness portion of said upper sidewall portion of said sidewall spacer structure while leaving a second thickness portion of said upper sidewall portion of said sidewall spacer structure above said recessed sacrificial material.
19. The method of claim 15 , further comprising, prior to depositing said sacrificial material, depositing a silicon-containing material layer above said at least one material layer so as to at least completely fill said gate cavity and thereafter performing an annealing process in the presence of said silicon-containing material layer.
20. The method of claim 15 , further comprising, after performing said spacer trimming process, removing said recessed sacrificial material from said gate cavity.
21. The method of claim 15 , wherein forming said at least one material layer comprises depositing a gate insulation layer comprising a high-k dielectric material and thereafter forming a metal layer comprising a work function adjusting material above said gate insulation layer.
22. A method, comprising:
forming a sacrificial gate structure above an active area of a semiconductor device;
forming a sidewall spacer structure adjacent sidewalls of said sacrificial gate structure;
performing at least one first etching process to remove said sacrificial gate structure selectively to said sidewall spacer structure so as to form a gate cavity defined by internal surfaces of said sidewall spacer structure, an upper portion of said gate cavity having a first opening width;
depositing at least one material layer in said gate cavity;
forming a recessed layer of sacrificial material in said gate cavity and above said at least one material layer, said recessed layer of sacrificial material exposing a first upper sidewall portion of said at least one material layer;
performing at least one second etching process to remove said exposed first upper sidewall portion of said at least one material layer within said gate cavity in the presence of said recessed layer of sacrificial material and to expose said internal surfaces of a second upper sidewall portion of said sidewall spacer structure above said recessed layer of sacrificial material; and
performing at least one third etching process on said second upper sidewall portion of said sidewall spacer structure so as to remove a first thickness portion of said second upper sidewall portion while leaving a second thickness portion of said second upper sidewall portion and to increase a size of said upper portion of said gate cavity to a second opening width that is greater than said first opening width.
23. The method of claim 22 , wherein, after performing said at least one third etching process, said internal surfaces of said sidewall spacer structure have a stepped cross-sectional configuration.
24. The method of claim 22 , wherein, after performing said at least one third etching process, at least a portion of said second upper sidewall portion of said sidewall spacer structure above said recessed layer of sacrificial material has outwardly tapered internal surfaces.
25. The method of claim 22 , further comprising, prior to forming said recessed layer of sacrificial material, depositing a silicon-containing material layer above said at least one material layer so as to at least completely fill said gate cavity and thereafter performing an annealing process in the presence of said silicon-containing material layer.
26. The method of claim 22 , further comprising, after performing said at least one third etching process, removing said recessed layer of sacrificial material from said gate cavity.
27. The method of claim 22 , wherein forming said at least one material layer comprises depositing a gate insulation layer comprising a high-k dielectric material and thereafter forming a metal layer comprising a work function adjusting material above said gate insulation layer.