IP Library › Granted Patent US 9,275,957
Granted Patent B2
US 9,275,957 · App. 14/061,153 · Granted Mar 1, 2016

EM protected semiconductor die

Inventors: Michael J. Seddon (Gilbert, AZ); Francis J. Carney (San Tan Valley, AZ); Gordon M. Grivna (Mesa, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/552H01L21/76898H01L21/78H01L23/481H01L23/60H01L21/31144H01L23/3114H01L2224/0401H01L2924/13091
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Quick Facts
Patent No.
US 9,275,957
App. No.
14/061,153
Granted
Mar 1, 2016
Kind
B2
Abstract

In one embodiment, a semiconductor die is formed to have sloped sidewalls. A conductor is formed on the sloped sidewalls.

Claims (20)

1. A semiconductor die comprising:

a semiconductor substrate having a first surface and a second surface wherein the semiconductor substrate includes a bulk silicon semiconductor substrate and a silicon semiconductor material overlying the bulk silicon semiconductor substrate;

a doped region formed in at least a portion of the silicon semiconductor material;

an opening extending through the semiconductor die including through the bulk silicon semiconductor substrate and through the semiconductor material overlying the bulk silicon semiconductor substrate, the opening having sidewalls wherein the sidewalls include rough sidewalls and at least one sidewall is a sloped sidewall so that a width of a first end of the opening is greater than a width of an opposite end of the opening; and

a first conductor on the sloped sidewall.

2. The semiconductor die of claim 1 wherein the first conductor is on a second surface of the semiconductor die.

3. The semiconductor die of claim 2 further including a second conductor overlying the first surface with a first portion of the second conductor abutting the first conductor.

4. The semiconductor die of claim 3 wherein the second conductor is adjacent to the first end of the opening.

5. The semiconductor die of claim 1 wherein the first end of the opening is approximately two to ten microns wider than the width of the opposite end.

6. The semiconductor die of claim 1 wherein the first conductor is a metal including one of Au or a multi-layer metal or a multi-layer metal of Ti/NiV/Au or a multi-layer metal of Ti/Ni/Au or a multi-layer metal of TiW/Au.

7. The semiconductor die of claim 1 further including a second conductor overlying the first surface of the semiconductor substrate with a first portion of the second conductor abutting the first conductor.

8. The semiconductor die of claim 7 wherein the second conductor is a portion of a via.

9. The semiconductor die of claim 1 further including the semiconductor die having exterior sidewalls extending from the first surface to the second surface wherein at least one of the exterior sidewalls is a sloped exterior sidewall so that a width of the first surface is greater than a width of the second surface; and

the first conductor on the sloped exterior sidewall wherein at least a first portion of the first conductor forms an electrical connection to the sloped exterior sidewall.

10. The semiconductor die of claim 1 wherein the second end of the opening is at the second surface.

11. The semiconductor die of claim 9 further including a second conductor overlying the first surface of the semiconductor substrate with a portion of the second conductor extending to the sloped sidewall to abut the first conductor and form an electrical connection therebetween.

12. The semiconductor die of claim 7 further including a third conductor on the first surface and abutting the second conductor.

13. The semiconductor die of claim 1 wherein the first conductor includes a metal.

14. The semiconductor die of claim 1 wherein the opening is formed as at least a portion of forming another opening through the semiconductor substrate to singulate the semiconductor die from other semiconductor die formed on a semiconductor wafer.

15. The semiconductor die of claim 1 wherein the first opening extends from the first surface of the semiconductor substrate through the semiconductor substrate to the second surface of the semiconductor substrate.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2013
From: SEDDON, MICHAEL J.; CARNEY, FRANCIS J.; GRIVNA, GORDON M.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 031462/0039 →
Continuity (2)
Division 12689137 · Jan 18, 2010
Related Publication 20140048917A1 · Feb 20, 2014