Method for fabricating semiconductor device with paterned hard mask
A method for fabricating a semiconductor device includes the following steps. First, a first interlayer dielectric is formed on a substrate. Then, a gate electrode is formed on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric. Afterwards, a patterned mask layer is formed on the gate electrode, and a bottom surface of the patterned mask layer is level with a top surface of the first interlayer dielectric. A spacer is then formed on each sidewall of the gate electrode. Subsequently, a second interlayer dielectric is formed to cover a top surface and each side surface of the patterned mask layer. Finally, a self-aligned contact structure is formed in the first interlayer dielectric and the second interlayer dielectric.
1. A method for fabricating a semiconductor device, comprising:
forming a first interlayer dielectric on a substrate;
forming a gate electrode on the substrate, wherein a periphery of the gate electrode is surrounded by the first interlayer dielectric;
forming a patterned mask layer directly on the gate electrode, wherein a bottom surface of the patterned mask layer is substantially level with a top surface of the first interlayer dielectric;
forming a spacer on each sidewall of the gate electrode after the step of forming the patterned mask layer;
forming a second interlayer dielectric to cover a top surface and sidewalls of the patterned mask layer; and
forming a self-aligned contact structure in the first interlayer dielectric and the second interlayer dielectric.
2. The method of claim 1 , further comprising:
forming a dummy gate electrode on the substrate;
removing the dummy gate electrode to leave a trench;
forming a gate electrode in the trench;
depositing a metal layer to fill up the trench; and
removing a portion of the metal layer until the first interlayer dielectric is exposed.
3. The method of claim 2 , further comprising:
forming a gate spacer on each sidewall of the dummy gate electrode;
conformally depositing an etch stop layer on each of the gate spacers; and
forming the self-aligned contact structure in the first interlayer dielectric and the second interlayer dielectric so that the self-aligned contact structure directly contacts the etch stop layer.
4. The method of claim 1 , wherein the top surface of the first interlayer dielectric is substantially level with the top surface of the gate electrode before the step of forming the patterned mask layer.
5. The method of claim 1 , further comprising:
depositing a mask layer to directly cover atop surface of the gate electrode; and
etching the mask layer until the patterned mask layer is formed.
6. The method of claim 1 , wherein a width of the patterned mask layer is substantially greater than a width of the gate electrode.
7. The method of claim 1 , wherein the spacer covers sidewalls of the patterned mask layer.
8. The method of claim 7 , wherein the spacer has a stack structure consisting of an oxide layer and a nitride layer from bottom to top.
9. The method of claim 1 , wherein the step of forming the spacer comprises:
conformally depositing a dielectric layer on the patterned mask layer; and
etching the dielectric layer to expose the first interlayer dielectric.
10. The method of claim 1 , wherein the step of forming the self-aligned contact structure comprises:
sequentially etching the second interlayer dielectric, the patterned mask layer and the first interlayer dielectric to form a contact hole, wherein the contact hole exposes a region of the substrate;
forming a silicide in the region; and
forming a metal layer to fill up the contact hole.
11. The method of claim 1 , wherein the self-aligned contact structure directly contacts the patterned mask layer.