IP Library › Granted Patent US 9,281,382
Granted Patent B2
US 9,281,382 · App. 14/295,618 · Granted Mar 8, 2016

Method for making semiconductor device with isolation pillars between adjacent semiconductor fins

Inventors: Qing Liu (Watervliet, NY); Ruilong Xie (Schenectady, NY); Xiuyu Cai (Niskayuna, NY); Chun-chen Yeh (Clifton Park, NY)
Assignees: STMICROELECTRONICS, INC.; GLOBALFOUNDRIES INC; INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/66795H01L21/76224H01L29/0649H01L29/785
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Quick Facts
Patent No.
US 9,281,382
App. No.
14/295,618
Granted
Mar 8, 2016
Kind
B2
Abstract

A method for making a semiconductor device may include forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins, and forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins. The method may further include selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material, and forming a region of a second dielectric material different than the first dielectric in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.

Claims (38)

1. A method for making a semiconductor device comprising:

forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins;

forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins;

selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material; and

forming a region of a second dielectric material different than the first dielectric material in the at least one trench to provide at least one isolation pillar between adjacent semiconductor fins.

2. The method of claim 1 wherein selectively removing the at least one intermediate semiconductor fin comprises selectively removing a group of adjacent intermediate semiconductor fins, and wherein the at least one isolation pillar comprises a group of spaced-apart isolation pillars.

3. The method of claim 1 further comprising selectively removing portions of the first dielectric material to widen the at least one trench after selectively removing the at least one intermediate semiconductor fin.

4. The method of claim 1 further comprising removing upper portions of the regions of the first dielectric material so that the semiconductor fins and the at least one isolation pillar extend above the regions of the first dielectric material.

5. The method of claim 1 wherein the first dielectric material comprises silicon dioxide, and wherein the second dielectric material comprises aluminum oxide.

6. The method of claim 1 further comprising forming a gate overlying the semiconductor fins and the at least one isolation pillar.

7. The method of claim 1 further comprising forming a pair of source and drain regions on opposing ends of at least one of the semiconductor fins.

8. The method of claim 1 wherein selectively removing the at least one intermediate semiconductor fin comprises forming a mask layer above the semiconductor fins and exposing the at least one intermediate semiconductor fin, and removing the at least one semiconductor fin through the mask layer.

9. The method of claim 1 further comprising:

forming a respective nitride region over each of the semiconductor fins; and

removing the nitride region over the at least one intermediate semiconductor fin using an isotropic etch prior to removing the at least one intermediate semiconductor fin.

10. The method of claim 1 wherein the plurality of semiconductor fins comprise silicon.

11. The method of claim 1 wherein the substrate comprises a semiconductor substrate.

12. A method for making a semiconductor device comprising:

forming, above a substrate, a plurality of laterally spaced-apart semiconductor fins;

forming regions of a first dielectric material between the laterally spaced-apart semiconductor fins;

selectively removing at least one intermediate semiconductor fin from among the plurality of semiconductor fins to define at least one trench between corresponding regions of the first dielectric material;

selectively removing portions of the first dielectric material to widen the at least one trench; and

forming regions of a second dielectric material different than the first dielectric material in the at least one trench to provide a group of spaced-apart isolation pillars between adjacent semiconductor fins.

13. The method of claim 12 further comprising removing upper portions of the regions of the first dielectric material so that the semiconductor fins and isolation pillars extend above the regions of the first dielectric material.

14. The method of claim 12 wherein the first dielectric material comprises silicon dioxide, and wherein the second dielectric material comprises aluminum oxide.

15. The method of claim 12 further comprising forming a gate overlying the semiconductor fins and the at least one isolation pillar, and forming a pair of source and drain regions on opposing ends of at least one of the semiconductor fins.

16. The method of claim 12 further comprising forming a pair of source and drain regions on opposing ends of at least one of the semiconductor fins.

17. The method of claim 12 wherein selectively removing the at least one intermediate semiconductor fin comprises forming a mask layer above the semiconductor fins and exposing the at least one intermediate semiconductor fin, and removing the at least one semiconductor fin through the mask layer.

18. A method for making a semiconductor device comprising:

forming, above a substrate, a plurality of laterally spaced-apart silicon fins;

forming regions of silicon oxide between the laterally spaced-apart silicon fins;

selectively removing at least one intermediate silicon fin from among the plurality of silicon fins to define at least one trench between corresponding regions of the silicon oxide; and

forming a region of aluminum oxide in the at least one trench to provide at least one isolation pillar between adjacent silicon fins.

19. The method of claim 18 wherein selectively removing the at least one intermediate silicon fin comprises selectively removing a group of adjacent intermediate silicon fins, and wherein the at least one isolation pillar comprises a group of spaced-apart isolation pillars.

20. The method of claim 18 further comprising selectively removing portions of the silicon oxide to widen the at least one trench after selectively removing the at least one intermediate silicon fin.

21. The method of claim 18 further comprising removing upper portions of the regions of the silicon oxide so that the silicon fins and the at least one isolation pillar extend above the regions of the silicon oxide.

22. The method of claim 18 further comprising forming a gate overlying the silicon fins and the at least one isolation pillar.

23. The method of claim 18 further comprising forming a pair of source and drain regions on opposing ends of at least one of the silicon fins.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2014
From: LIU, QING
To: STMICROELECTRONICS, INC.
Reel/Frame 033057/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2014
From: YEH, CHUN-CHEN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 033057/0452 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2014
From: XIE, RUILONG; CAI, XIUYU
To: GLOBALFOUNDRIES INC
Reel/Frame 033057/0403 →
Continuity (1)
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