Wafer level packaging method
A wafer level packaging method entails providing electronic devices and providing a platform structure having cavities extending through the platform structure. The platform structure is mounted to a temporary support. One or more electronic devices are placed in the cavities with an active side of each electronic device facing the temporary support. The platform structure and the electronic devices are encapsulated in an encapsulation material to produce a panel assembly. Redistribution layers may be formed over the panel assembly, after which the panel assembly may be separated into a plurality of integrated electronic packages. The platform structure may be formed from a semiconductor material, and platform segments within each package provide a fan-out region for conductive interconnects, as well as provide a platform for a metallization layer and/or for forming through silicon vias.
1. A method comprising:
providing a platform structure having a plurality of cavities extending through a thickness of said platform structure, said cavities being sized to accept electronic devices, wherein said platform structure comprises a semiconductor material;
mounting said platform structure to a temporary support;
placing said electronic devices in said cavities of said platform structure;
encapsulating said platform structure and said electronic devices in an encapsulation material to produce a panel assembly containing said electronic devices and said platform structure, wherein following said encapsulating, said method further comprises:
removing said panel assembly from said temporary support to expose an active side of each of said electronic devices at which electrical contacts are located;
applying at least one insulating layer over said active side of said each of said electronic devices;
forming openings in said at least one insulating layer to expose at least some of said electrical contacts on said active side of said each of said electronic devices;
providing conductive interconnects over said at least one insulating layer and extending through at least some of said openings in said at least one insulating layer;
separating said panel assembly into a plurality of integrated electronic packages following said providing said conductive interconnects, wherein for each of said integrated electronic packages, said separating exposes one of said conductive interconnects at a side wall of said each integrated electronic package; and
for said each of said integrated electronic packages, forming a conductive trace extending along said side wall, said conductive trace being in electrical communication with said one of said conductive interconnects.
2. The method of claim 1 wherein said providing comprises providing said platform structure with said cavities having a curvilinear shape.
3. The method of claim 1 wherein said providing comprises forming said platform structure from said semiconductor material having a first coefficient of thermal expansion (CTE) that is less than a second CTE of said encapsulation material.
4. The method of claim 1 wherein said providing comprises forming said platform structure from a material having a particle size of no greater than five microns.
5. The method of claim 1 wherein:
said placing comprises placing said electronic devices in said cavities so that gaps are located between device edges of said electronic devices and cavity edges of said cavities in said platform structure; and
said encapsulating comprises providing said encapsulation material in said gaps.
6. The method of claim 1 wherein:
said mounting comprises mounting said platform structure with a first surface of said platform structure facing said temporary support; and
said method further comprises exposing a second surface of said platform structure from said encapsulation material, said second surface opposing said first surface.
7. The method of claim 1 further comprising forming conductive vias extending through said platform structure.
8. The method of claim 1 wherein said integrated electronic packages are first integrated electronic packages and for each of said first integrated electronic packages, said method further comprises:
coupling a second integrated electronic package to one of a top exterior surface and a bottom exterior surface of said first integrated electronic package; and
electrically interconnecting said conductive trace extending along said side wall of said first integrated electronic package with a second electronic device of said second integrated electronic package.
9. The method of claim 1 wherein said separating occurs through said platform structure so that a portion of said platform structure is exposed at said side wall of each of said integrated electronic packages.
10. A method comprising:
providing a platform structure having a plurality of cavities extending through a thickness of said platform structure, said cavities being sized to accept electronic devices, wherein said platform structure comprises a semiconductor material;
forming conductive vias extending through said platform structure;
mounting said platform structure to a temporary support;
placing said electronic devices in said cavities of said platform structure;
encapsulating said platform structure and said electronic devices in an encapsulation material to produce a panel assembly containing said electronic devices, said platform structure, and said conductive vias; and
separating said panel assembly into a plurality of integrated electronic packages following said encapsulating, said separating occurring through said platform structure so that a portion of said platform structure is exposed at opposing side walls of each of said integrated electronic packages, wherein prior to said separating, said method further comprises:
removing said panel assembly from said temporary support to expose an active side of each of said electronic devices at which electrical contacts are located;
applying at least one insulating layer over said active side of said each of said electronic devices and over a non-cavity area of said platform structure surrounding said active side of said each of said electronic devices;
forming openings in said at least one insulating layer to expose at least some of said electrical contacts on said active side of said each of said electronic devices;
forming said openings in said at least one insulating layer overlying said non-cavity area of said platform structure; and
providing conductive interconnects over said at least one insulating layer and extending through at least some of said openings in said at least one insulating layer.
11. A method comprising:
providing a platform structure having a plurality of cavities extending through a thickness of said platform structure, said cavities being sized to accept electronic devices, wherein said platform structure comprises a semiconductor material;
forming conductive vias extending through said platform structure;
mounting said platform structure to a temporary support;
placing said electronic devices in said cavities of said platform structure;
encapsulating said platform structure and said electronic devices in an encapsulation material to produce a panel assembly containing said electronic devices, said platform structure, and said conductive vias, wherein following said encapsulating, said method further comprises:
removing said panel assembly from said temporary support to expose an active side of each of said electronic devices at which electrical contacts are located;
applying at least one insulating layer over said active side of said each of said electronic devices;
forming openings in said at least one insulating layer to expose at least some of said electrical contacts on said active side of said each of said electronic devices; and
providing conductive interconnects over said at least one insulating layer and extending through at least some of said openings in said at least one insulating layers;
separating said panel assembly into a plurality of integrated electronic packages following said encapsulating, said separating occurring through said platform structure so that a portion of said platform structure is exposed at opposing side walls of each of said integrated electronic packages, wherein following said providing said conductive interconnects, said separating exposes one of said conductive interconnects at a side wall of said each integrated electronic package; and
for said each of said integrated electronic packages, forming a conductive trace extending over said portion of said platform structure at said side wall, said conductive trace being in electrical communication with said one of said conductive interconnects.