Electronic devices and components for high efficiency power circuits

1. A method of forming an electronic component, comprising:

providing a pair of transistors, wherein a first transistor of the pair of transistors is a III-N transistor;

providing a rectifying device;

enclosing the pair of transistors and the rectifying device in a single package;

electrically connecting a gate electrode of the III-N transistor to a first lead of the single package or to a conductive structural portion of the single package,

electrically connecting a drain electrode of the III-N transistor to a second lead of the single package and to a first electrode of the rectifying device, and

electrically connecting a second electrode of the rectifying device to a third lead of the single package.

2. The method of claim 1 , wherein the III-N transistor is a field-effect transistor.

3. The method of claim 1 , wherein the III-N transistor is a high voltage switching transistor.

4. The method of claim 1 , wherein a second transistor of the pair of transistors is an enhancement-mode device.

5. The method of claim 1 , wherein the rectifying device is provided as a III-N rectifying device.

6. The method of claim 5 , wherein the III-N rectifying device is a III-N diode, the first electrode is an anode electrode, and the second electrode is a cathode electrode.

7. The method of claim 6 , wherein the III-N transistor is a lateral device comprising an insulating or semi-insulating portion, and the insulating or semi-insulating portion is mounted directly to the conductive structural portion of the single package, without an insulating spacer between the III-N transistor and the conductive structural portion of the single package.

8. The method of claim 7 , wherein the insulating or semi-insulating portion is an insulating or semi-insulating substrate.

9. The method of claim 6 , wherein the III-N transistor is a lateral device comprising a conducting or semi-conducting substrate, and an insulating or semi-insulating III-N layer is between the conducting or semi-conducting substrate and a channel of the III-N transistor, wherein the conducting or semi-conducting substrate is mounted directly to the conductive structural portion of the single package, without an insulating spacer between the III-N transistor and the conductive structural portion of the single package.

10. The method of claim 9 , wherein the conducting or semi-conducting substrate is a semi-conducting silicon substrate.

11. The method of claim 6 , wherein the III-N transistor and the III-N diode are on a common substrate.

12. The method of claim 6 , wherein the III-N diode is a lateral device comprising a conducting or semi-conducting substrate, and an insulating or semi-insulating III-N layer is between the conducting or semi-conducting substrate and a channel of the III-N diode, wherein the conducting or semi-conducting substrate is mounted directly to the conductive structural portion of the single package, without an insulating spacer between the III-N diode and the conductive structural portion of the single package.

13. The method of claim 12 , wherein the conducting or semi-conducting substrate is a semi-conducting silicon substrate.

14. The method of claim 6 , wherein the III-N diode is a lateral device comprising an insulating or semi-insulating portion, and the insulating or semi-insulating portion is mounted directly to the conductive structural portion of the single package, without an insulating spacer between the III-N diode and the conductive structural portion of the single package.

15. The method of claim 14 , wherein the insulating or semi-insulating portion is an insulating or semi-insulating substrate.

16. The method of claim 1 , wherein the III-N transistor is a first III-N transistor and the rectifying device is provided as a second III-N transistor.

17. The method of claim 16 , wherein the first III-N transistor or the second III-N transistor is a lateral device comprising an insulating or semi-insulating portion, and the insulating or semi-insulating portion is mounted directly to the conductive structural portion of the single package without an insulating spacer between the first III-N transistor and the conductive structural portion of the single package or between the second III-N transistor and the conductive structural portion of the single package.

18. The method of claim 17 , wherein the insulating or semi-insulating portion is an insulating or semi-insulating substrate.

19. The method of claim 16 , wherein the first III-N transistor or the second III-N transistor is a lateral device comprising a conducting or semi-conducting substrate, and an insulating or semi-insulating III-N layer between the conducting or semi-conducting substrate and a channel of the first III-N transistor or the second III-N transistor, wherein the conducting or semi-conducting substrate is mounted directly to the conductive structural portion of the single package, without an insulating spacer between the first III-N transistor and the conductive structural portion of the single package or between the second III-N transistor and the conductive structural portion of the single package.

20. The method of claim 19 , wherein the conducting or semi-conducting substrate is a semi-conducting silicon substrate.

21. The method of claim 16 , wherein the first III-N transistor and the second III-N transistor are formed on a common substrate.

22. The method of claim 1 , further comprising connecting a source electrode of a second transistor of the pair of transistors to the conductive structural portion of the single package or to a source lead of the single package.

23. The method of claim 1 , wherein the III-N transistor is a III-N depletion-mode transistor, and a second transistor of the pair of transistors is an enhancement-mode transistor, the enhancement-mode transistor comprising an e-mode transistor source electrode, an e-mode transistor gate electrode, and an e-mode transistor drain electrode, wherein the e-mode transistor source electrode is electrically connected to the conductive structural portion of the single package or to a source lead of the single package, the e-mode transistor drain electrode is electrically connected to a source electrode of the III-N depletion-mode transistor, and the e-mode transistor gate electrode is electrically connected to the first lead of the single package.

24. The method of claim 23 , wherein the III-N depletion-mode transistor is a high-voltage switching transistor, and the enhancement-mode transistor is a low-voltage transistor.

25. The method of claim 24 , wherein the enhancement-mode transistor is a Si MOS device.

26. The method of claim 1 , wherein the electronic component is a part of a voltage converter.

27. A method of forming an electronic component, comprising:

providing a III-N depletion-mode transistor;

providing an enhancement-mode transistor;

providing a rectifying device;

enclosing each of the III-N depletion-mode transistor, the enhancement-mode transistor, and the rectifying device in a single package, and

electrically connecting a gate electrode of the III-N depletion-mode transistor to a source electrode of the enhancement-mode transistor, electrically connecting a source electrode of the III-N depletion-mode transistor to a drain electrode of the enhancement-mode transistor, electrically connecting a drain electrode of the III-N depletion-mode transistor to a second lead of the single package and to a first electrode of the rectifying device, and electrically connecting a second electrode of the rectifying device to a first lead of the single package.

28. The method of claim 27 , wherein the enhancement-mode transistor is a Si MOS device.

29. The method of claim 28 , wherein the rectifying device comprises a III-N transistor.

30. The method of claim 27 , wherein the rectifying device is a III-N diode, the first electrode is an anode electrode, and the second electrode is a cathode electrode.

31. The method of claim 27 , wherein the electronic component is a part of a voltage converter.

32. The method of claim 27 , wherein the III-N depletion-mode transistor and the rectifying device are on a common substrate.

33. A method of forming an electronic component, comprising:

providing a III-N depletion-mode transistor;

providing an enhancement-mode transistor;

providing a rectifying device; and

enclosing each of the III-N depletion-mode transistor, the enhancement-mode transistor, and the rectifying device in a single package, the single package comprising a first lead and a second lead; wherein

a gate electrode of the III-N depletion-mode transistor is electrically connected to the first lead of the single package or to a conductive structural portion of the single package, a source electrode of the III-N depletion-mode transistor is electrically connected to a drain electrode of the enhancement-mode transistor, a drain electrode of the III-N depletion-mode transistor is electrically connected to a first electrode of the rectifying device, and a second electrode of the rectifying device is electrically connected to the second lead of the single package.

34. The method of claim 33 , wherein the drain electrode of the III-N depletion-mode transistor is also electrically connected to a third lead of the single package.

35. The method of claim 33 , wherein the rectifying device comprises a diode, and the first electrode of the rectifying device comprises an anode.

36. The method of claim 33 , wherein the electronic component is a part of a voltage converter.

37. The method of claim 33 , wherein the III-N depletion-mode transistor and the rectifying device are on a common substrate.

38. The method of claim 33 , wherein the drain electrode of the III-N depletion-mode transistor is electrically connected to the second lead of the single package.