Method of dynamically selecting memory cell capacity
A method is provided for using a multi-level cell memory device. The method includes writing first data to a first portion of a memory array using a first number of state levels for memory cells of the first portion of the memory array. The method further includes re-writing second data to a second portion of the memory array using a second number of state levels for memory cells of the second portion of the memory array. The second number is different from the first number.
1. A method of using a multi-level cell memory device, the method comprising:
responsive to a first instruction, writing first data to a first portion of a memory array using a first number of threshold voltage values corresponding to a respective first number of states, wherein the first instruction includes a first operating parameter indicating particular values of the first number of threshold voltage values; and
responsive to a second instruction, writing second data to a second portion of the memory array using a second number of threshold voltage values corresponding to a respective second number of states, wherein the second instruction includes a second operating parameter indicating particular values of the second number of threshold values, and wherein the second number of states is different from the first number of states.
2. The method of claim 1 , wherein the first instruction comprises a first write-command and the first operating parameter, and wherein the second instruction comprises a second write command and the second operating parameter, wherein at least one of the number of first threshold voltage values is different than at least one of the second threshold voltage values.
3. The method of claim 2 , further comprising:
reading the first data from the first portion of the memory array in response to receiving a third instruction comprising a first read command and at least the first operating parameter; and
reading the second data from the second portion of the memory array in response to receiving a fourth instruction comprising a second read command and at least the second operating parameter.
4. The method of claim 1 , further comprising, subsequent to writing the first data to the first portion of the memory array using the particular values of the first number of threshold voltage values, writing third data to the first portion of the memory array using the particular values of the second number of threshold voltage values.
5. The method of claim 4 , wherein writing the third data to the first portion of the memory array is performed in response to receiving a fifth instruction comprising a third write command and at least the second operating parameter.
6. The method of claim 5 , further comprising reading the third data from the first portion of the memory array in response to receiving a sixth instruction comprising a third write command and at least the second operating parameter.
7. The method of claim 1 , wherein the first number of states is two and the second number of states is either three or four.
8. The method of claim 1 , further comprising writing third data to a third portion of the memory array using a third number of threshold voltage values corresponding to a respective third number of states, the third number of states is different from the second number of states and different from the first number of states.
9. The method of claim 8 , wherein writing third data to the third portion of the memory array is performed in response to receiving a third instruction comprising a third write command and at least a third operating parameter indicating particular values of the third number of threshold values.
10. A memory device comprising:
a plurality of multi-level memory cells; and
circuitry to:
responsive to a first instruction, write first data to a first portion of a memory array using a first number of threshold voltage values corresponding to a respective first number of states, wherein the first instruction includes a first operating parameter indicating particular values of the first number of threshold voltage values; and
responsive to a second instruction, write second data to a second portion of the memory array using a second number of threshold voltage values corresponding to a respective second number of states, wherein the second instruction includes a second operating parameter indicating particular values of the second number of threshold values, wherein the second number of states is different from the first number of states.
11. The memory device of claim 10 , wherein the first instruction comprises a first write command and the first operating parameter, wherein the second instruction comprises a second write command the second operating, wherein at least one of the number of first threshold voltage values is different than at least one of the second threshold values.
12. The memory device of claim 11 , wherein the circuitry further:
reads the first data from the first portion of the memory array in response to receiving a third instruction comprising a first read command and at least the first operating parameter; and
reads the second data from the second portion of the memory array in response to receiving a fourth instruction comprising a second read command and at least the second operating parameter.
13. The memory device of claim 10 , wherein the circuitry, subsequent to writing the first data to the first portion of the memory array using the first number of threshold voltage values, writes third data to the first portion of the memory array using the second number of threshold voltage values.
14. The memory device of claim 13 , wherein the circuitry writes the third data to the first portion of the memory array in response to receiving a fifth instruction comprising a third write command and at least the second operating parameter.
15. A memory system comprising:
a memory device comprising a plurality of multi-level memory cells and a memory controller to:
responsive to a first instruction, write first data to a first portion of a memory array using a first number of threshold voltage values corresponding to a respective first number of states, wherein the first instruction includes a first operating parameter indicating particular values of the first threshold voltage values;
responsive to a second instruction, write second data to a second portion of the memory array using a second number of threshold voltage values corresponding to a respective second number of states, wherein the second instruction includes a second operating parameter indicating particular values of the second number of threshold values, and wherein the second number of states is different from the first number of states; and
a processor configured to provide access to the plurality of multi-level memory cells.
16. The memory system of claim 15 , wherein first instruction comprises a first write command and the first operating parameter, wherein the second instruction comprises a second write command and the second operating parameter, wherein at least one of the number of threshold voltage values is different than at least one of the second threshold voltage values.
17. The memory system of claim 16 , wherein the memory controller further:
reads the first data from the first portion of the memory array in response to receiving a third instruction comprising a first read command and at least the first operating parameter; and
reads the second data from the second portion of the memory array in response to receiving a fourth instruction comprising a second read command and at least the second operating parameter.
18. The memory system of claim 15 , wherein the memory controller, subsequent to writing the first data to the first portion of the memory array using the first number of threshold voltage values, writes third data to the first portion of the memory array using the second number of threshold voltage values.
19. The memory system of claim 18 , wherein the memory controller writes the third data to the first portion of the memory array in response to receiving a fifth instruction comprising a third write command and the at least the second operating parameter.