Vertical fin eDRAM
Systems and methods of forming semiconductor devices. A trench capacitor comprising deep trenches is formed in an n+ type substrate. The deep trenches have a lower portion partially filled with a trench conductor surrounded by a storage dielectric. A polysilicon growth is formed in an upper portion of the deep trenches. The semiconductor device includes a single-crystal semiconductor having an angled seam separating a portion of the polysilicon growth from an exposed edge of the deep trenches. A word-line is wrapped around the single-crystal semiconductor. A bit-line overlays the single-crystal semiconductor.
1. A semiconductor device comprising:
a trench capacitor comprising deep trenches formed in a n+ type substrate, said deep trenches having a lower portion partially filled with a trench conductor surrounded by a storage dielectric;
a polysilicon growth formed in an upper portion of said deep trenches;
a single-crystal semiconductor having a seam separating a portion of said polysilicon growth from an exposed edge of said deep trenches, said seam being at an acute angle from said exposed edge;
a word-line wrapped around said single-crystal semiconductor; and
a bit-line overlaying said single-crystal semiconductor.
2. The semiconductor device according to claim 1 , further comprising:
a buried oxide (BOX) layer, and
a silicon on oxide (SOI) layer,
said trench conductor extending into said BOX layer.
3. The semiconductor device according to claim 2 , said seam separating a portion of said polysilicon growth and an exposed edge of said SOI layer.
4. The semiconductor device according to claim 2 , said single-crystal semiconductor being selectively grown from said SOI layer.
5. The semiconductor device according to claim 1 , further comprising:
fins formed in said single-crystal semiconductor; and
nodes comprising doped silicon epitaxially grown on exposed ends of said fins,
said bit-line contacting said nodes.
6. The semiconductor device according to claim 1 , further comprising at least one oxide layer between said word-line and said bit-line.
7. The semiconductor device according to claim 1 , further comprising:
a gate stack comprising:
said word-line;
an insulator layer; and
a doped silicon node contacting said bit-line.
8. A semiconductor device comprising:
a substrate comprising:
a silicon layer,
a buried oxide (BOX) layer, and
a silicon on oxide (SOI) layer, said BOX layer being between said silicon layer and said SOI layer;
a trench capacitor comprising deep trenches through said BOX layer and said SOI layer and partially into said silicon layer, said deep trenches having a lower portion partially filled with a trench conductor surrounded by a storage dielectric, said trench conductor extending into said BOX layer;
a polysilicon growth extending from said trench conductor in an upper portion of said deep trenches;
a single-crystal semiconductor extending from an exposed edge of said SOI layer; and
a seam separating a portion of said polysilicon growth from said exposed edge of said SOI layer.
9. The semiconductor device according to claim 8 , said seam being at an acute angle from said exposed edge.
10. The semiconductor device according to claim 8 , further comprising:
fins formed in said single-crystal semiconductor.
11. The semiconductor device according to claim 10 , further comprising:
nodes comprising doped silicon epitaxially grown on exposed ends of said fins.
12. The semiconductor device according to claim 11 , further comprising:
a bit-line contacting said nodes.
13. The semiconductor device according to claim 12 , further comprising:
a word-line wrapped around said single-crystal semiconductor.
14. The semiconductor device according to claim 13 , further comprising an oxide layer between said word-line and said bit-line.