Fabricating stacked nanowire, field-effect transistors
Methods are presented for facilitating fabricating stacked nanowire, field-effect transistors. The methods include: forming a cut mask spacer on a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along its sidewalls, and the cut mask spacer overlying the sidewall spacer; defining a stack structure by cutting through the multiple layers using the cut mask spacer and gate structure as a mask, and selectively etching at least one layer of the multiple layers to undercut, in part, the mask, where at least one other layer of the multiple layers remains un-etched by the selectively etching; and providing an alignment mask spacer over the gate structure and over end surfaces of the multiple layers below the gate structure, the alignment mask spacer facilitating etching the other layer(s) of the multiple layers to selectively expose, in part, end surfaces of the other layer(s).
1. A semiconductor structure comprising:
a gate structure disposed above multiple layers above a substrate structure, the gate structure including a sidewall spacer along sidewalls thereof;
a stack structure formed by the multiple layers and the gate structure; and
an alignment mask spacer located alongside and covering a portion of the sidewall spacer and gate structure, the alignment mask spacer being located over surfaces of the multiple layers and below at least a portion of the sidewall spacer and gate structure, the alignment mask spacer facilitating etching the at least one other layer of the multiple layers to selectively expose the end surfaces thereof.
2. The semiconductor structure of claim 1 , wherein the multiple layers comprise a first semiconductor material layer and a second semiconductor material layer, wherein the at least one layer of the multiple layers selectively etched comprises the second semiconductor material layer, and the at least one other layer of the multiple layers comprises the first semiconductor material layer.
3. The semiconductor structure of claim 2 , wherein the first semiconductor material layer comprises silicon, and the second semiconductor material layer comprises germanium or silicon-germanium.
4. The semiconductor structure of claim 1 , wherein the multiple layers comprise multiple, alternating first and second semiconductor material layers.
5. The semiconductor structure of claim 4 , wherein the multiple second semiconductor material layers comprise the at least one layer of the multiple layers.
6. The semiconductor structure of claim 5 , wherein the multiple second semiconductor material layers comprise germanium or silicon-germanium.
7. The semiconductor structure of claim 4 , wherein the multiple first semiconductor layers comprise the at least one other layer of the multiple layers.
8. The semiconductor structure of claim 7 , wherein the multiple first semiconductor materials layers comprise silicon.
9. The semiconductor structure of claim 4 , wherein at least one second semiconductor material layer of the multiple second semiconductor material layers has a greater thickness than at least one first semiconductor material layer of the multiple first semiconductor material layers.
10. The semiconductor structure of claim 9 , wherein the alignment mask spacer is conformally wrapped around exposed portions of the multiple first semiconductor material layers of the multiple, alternating first and second semiconductor material layers.
11. The semiconductor structure of claim 1 , wherein the alignment mask spacer comprises a nitride spacer.
12. The semiconductor structure of claim 1 , wherein the sidewall spacer comprises one of a nitride spacer or a low-k dielectric constant spacer.
13. The semiconductor structure of claim 1 , wherein the substrate structure comprises an insulating layer disposed over a substrate, the multiple layers and the gate structure being disposed above the insulating layer.
14. The semiconductor structure of claim 1 , wherein portions of the at least one of said multiple layers form nanowire structures.
15. The semiconductor structure of claim 1 , wherein the alignment mask spacer covers the entire sidewall spacer.
16. The semiconductor structure of claim 15 , wherein the alignment mask spacer is conformally wrapped around exposed portions of the multiple first semiconductor material layers of the multiple, alternating first and second semiconductor material layers.
17. The semiconductor structure of claim 15 , wherein the alignment mask spacer comprises a nitride spacer.
18. The semiconductor structure of claim 15 , wherein the sidewall spacer comprises one of a nitride spacer or a low-k dielectric constant spacer.
19. The semiconductor structure of claim 15 , wherein the substrate structure comprises an insulating layer disposed over a substrate, the multiple layers and the gate structure being disposed above the insulating layer.
20. The semiconductor structure of claim 15 , wherein portions of the at least one of said multiple layers form nanowire structures.