IP Library › Granted Patent US 9,508,743
Granted Patent B2
US 9,508,743 · App. 14/525,842 · Granted Nov 29, 2016

Dual three-dimensional and RF semiconductor devices using local SOI

Inventors: Jagar Singh (Clifton Park, NY); Srikanth Balaji Samavedam (Cohoes, NY)
Assignee: GLOBALFOUNDRIES INC.
H01L27/1211H01L21/7624H01L21/845H01L23/66H01L27/092H01L27/1207
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Quick Facts
Patent No.
US 9,508,743
App. No.
14/525,842
Granted
Nov 29, 2016
Kind
B2
Abstract

Co-fabrication of a radio-frequency (RF) semiconductor device with a three-dimensional semiconductor device includes providing a starting three-dimensional semiconductor structure, the starting structure including a bulk silicon semiconductor substrate, raised semiconductor structure(s) coupled to the substrate and surrounded by a layer of isolation material. Span(s) of the layer of isolation material between adjacent raised structures are recessed, and a layer of epitaxial semiconductor material is created over the recessed span(s) of isolation material over which another layer of isolation material is created. The RF device(s) are fabricated on the layer of isolation material above the epitaxial material, which creates a local silicon-on-insulator, while the three-dimensional semiconductor device(s) can be fabricated on the raised structure(s).

Claims (24)

1. A method, comprising:

providing a starting three-dimensional semiconductor structure, the starting structure comprising a bulk semiconductor substrate, a plurality of raised semiconductor structures coupled to the substrate and surrounded by a layer of isolation material;

recessing at least one span of the layer of isolation material between adjacent raised structures;

forming a layer of epitaxial semiconductor material over the recessed at least one span of isolation material;

forming another layer of isolation material over the layer of epitaxial material; and

fabricating one or more radio-frequency (RF) devices on the another layer of isolation material.

2. The method of claim 1 , wherein the one or more RF devices comprise one or more CMOS (complementary metal oxide semiconductor) RF devices.

3. The method of claim 1 , wherein the one or more RF devices comprise one or more planar RF devices.

4. The method of claim 1 , wherein the one or more RF devices comprise one or more three-dimensional RF devices.

5. The method of claim 1 , further comprising fabricating at least one three-dimensional semiconductor device on one or more of the plurality of raised structures.

6. The method of claim 5 , wherein fabricating the one or more radio-frequency devices is accomplished while fabricating the at least one three-dimensional semiconductor device.

7. The method of claim 1 , wherein the starting three-dimensional semiconductor structure further comprises a layer of hard mask material over each of the plurality of raised semiconductor structures, the method further comprising planarizing the isolation material using the hard mask material as a stop.

8. The method of claim 7 , further comprising, after providing the starting structure and before recessing the at least one span, masking the plurality of raised structures.

9. The method of claim 8 , wherein the masking comprises:

creating a blanket layer of hard mask material on a top surface of the planarized isolation material; and

removing a portion of the blanket layer of hard mask material above the at least one span.

10. The method of claim 7 , further comprising recessing the layer of isolation material and the another layer of isolation material down to between a top surface and a bottom surface of the layer of hard mask material over the plurality of raised structures.

11. The method of claim 1 , wherein the recessing comprises recessing the at least one span of the layer of isolation material below a top surface of the adjacent raised structures, exposing a top portion of the adjacent raised structures, and wherein creating the layer of epitaxial material comprises growing the epitaxial semiconductor material on the recessed at least one span of the layer of isolation material using the exposed top portion of the adjacent raised structures as a seed.

12. A three-dimensional semiconductor structure, comprising:

a semiconductor substrate;

a plurality of raised semiconductor structures coupled to the substrate, a layer of isolation material surrounding the plurality of raised structures;

at least one layer of epitaxial semiconductor material over a recessed span of the layer of isolation material between an upper portion of adjacent raised structures;

another layer of the isolation material over the at least one layer of epitaxial semiconductor material; and

at least one radio-frequency (RF) semiconductor device on the another layer of isolation material.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded May 12, 2021
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 056987/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: GLOBALFOUNDRIES INC.
To: GLOBALFOUNDRIES U.S. INC.
Reel/Frame 054633/0001 →
SECURITY AGREEMENT Recorded Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2014
From: SINGH, JAGAR; SAMAVEDAM, SRIKANTH BALAJI
To: GLOBALFOUNDRIES INC.
Reel/Frame 034052/0387 →
Continuity (1)
Related Publication 20160118414A1 · Apr 28, 2016