Block behavior tracking in a memory system
A storage device with a memory may include memory block health monitoring and behavior tracking. Each memory block may be analyzed based on one or more dummy wordlines within the block may not be accessible for normal data storage. The dummy wordlines may be programmed with a known data pattern that can be tracked and analyzed for potential errors, which may be used as representation of the health of the memory block. Adjustments can be made to the operating parameters (e.g. read voltages) to optimize each memory block based on its error analysis.
1. A method for determining a health of a block of memory comprising:
programming, by a command issued by a memory controller, a dummy wordline with a known data pattern, wherein the dummy wordline acts as a buffer for normal wordlines;
reading from the dummy wordline;
comparing the read out with the known data pattern;
determining whether any errors between read out and the known data pattern exceed a threshold; and
adjusting read parameters based on the errors.
2. The method of claim 1 wherein the read parameters comprise read voltage level.
3. The method of claim 2 wherein the adjusting the read parameters further comprises:
calculating, based on the errors, a charge loss or a charge gain;
decreasing, for a charge loss, the read voltage level; and
increasing, for a charge gain, the read voltage level.
4. The method of claim 3 wherein the charge gain represents a read disturb error or program disturb from charge leakage into a memory cell.
5. The method of claim 3 wherein the charge loss represents a data retention error.
6. The method of claim 3 wherein the calculating comprises using a known number of 0 bits and known number of 1 bits from the known data pattern and measuring a change to the number of 0 bits and a change to the number of 1 bits.
7. The method of claim 6 wherein the calculating comprises counting the 0 bits and 1 bits such that an increase in 0 bits is the charge gain and an increase in 1 bits is the charge loss.
8. The method of claim 7 wherein an amount of adjustment to the read voltage level is determined based on the change in the calculation.
9. The method of claim 8 wherein the amount of adjustment corresponds to a voltage amount that is determined by an approximation of stored electrons for the change in the 0 bit values.
10. The method of claim 1 wherein the dummy wordline is not accessible by a host for data storage.
11. The method of claim 1 wherein the method is performed with flash memory and the flash memory comprises a three-dimensional (3D) memory configuration, and wherein a controller is associated with operation of and storing to the flash memory.
12. A storage device comprising:
a non-volatile memory with blocks of memory, wherein each of the blocks includes one or dummy wordlines;
a pattern generation module that generates and stores a known data pattern on the one or more dummy wordlines;
an error analysis module that compares data stored on the one or more dummy wordlines with the known data pattern; and
a read parameter adjustment module that modifies a bias voltage based on the comparison.
13. The storage device of claim 12 wherein the known data pattern comprises a known number of 0 bits and a known number of 1 bits.
14. The storage device of claim 13 wherein the error analysis module comparison comprises a determination of whether there is an increase in 0 bits or an increase in 1 bits, wherein the increase in 0 bits is a charge gain and read disturb error, further wherein the increase in 1 bits is a charge loss and a data retention error.
15. The storage device of claim 14 wherein the read parameter adjustment module increases the bias voltage for the charge gain and decreases the bias voltage for the charge loss.
16. The storage device of claim 15 wherein an amount of change of the bias voltage is calculated based on a voltage amount that is determined by an approximation of stored electrons for the change in the 0 bit values and based on a capacitance value of the one or more dummy wordlines.
17. The storage device of claim 12 wherein the dummy wordline is a barrier to protect normal wordlines and is not accessible by a host for data storage.
18. A method for identifying errors in a block comprising:
storing a known data pattern on a dummy wordline of the block;
comparing the stored data on the dummy wordline with the known data pattern to identify any differences in 0 bits or 1 bits with the stored data;
identifying a read disturb error condition when a charge gain has occurred because of an increase in 0 bits and a decrease in 1 bits; and
identifying a data retention error condition when a charge loss has occurred because of an increase in 1 bits and a decrease in 0 bits.
19. The method of claim 18 further comprising:
updating a read bias based on the identification of the read disturb error or the data retention error.
20. The method of claim 19 wherein an amount of shift of the read bias corresponds to a change in charge divided by a capacitance of the dummy wordline, wherein the change in charge comprises a difference in an amount of electrons resulting from errors.
21. The method of claim 19 wherein the read bias comprises a bias for reading regular wordlines and the updating comprises adjusting the bias for reading the regular wordlines.
22. The method of claim 18 wherein the dummy wordline is a spacer outside of normal wordlines that is not accessible by a host for data storage.
23. The method of claim 18 further comprising:
selecting ECC power for data from the regular wordlines, wherein the selecting is based on the dummy wordline error.
24. A method for using a dummy wordline in a memory block, the method comprising:
utilizing a known data pattern on the dummy wordline, wherein the dummy wordline is not accessible by a host for data storage;
comparing data on the dummy wordline with the known data pattern; and
identifying errors based on the comparison, wherein the errors determine a health of the block.