IP Library Granted Patent US 9,559,077
Granted Patent B2
US 9,559,077 · App. 14/521,451 · Granted Jan 31, 2017

Die attachment for packaged semiconductor device

Inventors: Akhilesh K. Singh (Austin, TX); Rama I. Hegde (Austin, TX); Nishant Lakhera (Austin, TX)
Assignee: NXP USA, Inc.
H01L24/83H01L21/4828H01L23/49503H01L23/49513H01L23/49575H01L24/11H01L24/13H01L24/27H01L24/29H01L24/30H01L24/32H01L24/33H01L24/73H01L24/81H01L24/85H01L24/92H01L21/561H01L23/3107H01L24/16H01L24/48H01L2224/119H01L2224/1161H01L2224/11334H01L2224/11436H01L2224/131H01L2224/133H01L2224/13005H01L2224/1319H01L2224/1329H01L2224/13082H01L2224/13294H01L2224/16245H01L2224/2761H01L2224/27334H01L2224/27436H01L2224/291H01L2224/293H01L2224/2919H01L2224/2929H01L2224/29294H01L2224/30131H01L2224/3201H01L2224/32014H01L2224/32245H01L2224/32257H01L2224/32258H01L2224/3301H01L2224/33505H01L2224/48137H01L2224/48247H01L2224/48465H01L2224/48471H01L2224/73204H01L2224/73257H01L2224/73265H01L2224/8185H01L2224/81192H01L2224/81201H01L2224/81447H01L2224/81455H01L2224/81801H01L2224/8385H01L2224/83104H01L2224/83192H01L2224/83201H01L2224/83385H01L2224/83447H01L2224/83455H01L2224/83801H01L2224/83851H01L2224/83907H01L2224/85205H01L2224/85207H01L2224/92H01L2224/9205H01L2224/9222H01L2224/92227H01L2224/92247H01L2924/181
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Quick Facts
Patent No.
US 9,559,077
App. No.
14/521,451
Granted
Jan 31, 2017
Kind
B2
Abstract

A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.

Claims (28)

1. A method for forming a packaged semiconductor device, comprising:

attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate, wherein no bond pads are located on the first major surface, wherein a top surface of each protrusion has a die attach material, wherein the die attach material directly contacts the first major surface and the top surface of each protrusion, and wherein the attaching results in a space under exposed portions of the first major surface of the semiconductor die between the plurality of protrusions;

forming interconnects between bond pads located on a second major surface of the semiconductor die and the package substrate subsequent to the attaching, wherein the second major surface is opposite the first major surface;

filling the space with underfill material subsequent to the forming the interconnects; and

forming an encapsulant material over the semiconductor die and the interconnects subsequent to the filling the space.

2. The method of claim 1 , wherein the forming the encapsulant material is performed such that the encapsulant material contacts the second major surface of the semiconductor die and the underfill material contacts portions of the first major surface of the semiconductor die located between protrusions of the plurality of protrusions.

3. The method of claim 1 , wherein the die attach material comprises a pressure sensitive adhesive.

4. The method of claim 1 , wherein no curing is performed after the attaching the first major surface of the semiconductor die to the plurality of protrusions and before the forming the interconnects.

5. The method of claim 1 , wherein the package substrate is further characterized as a lead frame and the plurality of protrusions comprises a same material as the lead frame.

6. The method of claim 1 , wherein prior to the forming the interconnects, the method further comprises:

attaching a first major surface of a second semiconductor die to a second plurality of protrusions extending from the package substrate, wherein no bond pads are located on the first major surface of the second semiconductor die, wherein a top surface of each protrusion of the second plurality of protrusions has additional die attach material, and wherein the additional die attach material directly contacts the first major surface of the second semiconductor die and the top surface of each protrusion of the second plurality of protrusions.

7. The method of claim 6 , wherein the top surfaces of the second plurality of protrusions extend further from the package substrate than the top surfaces of the plurality of protrusions.

8. The method of claim 7 , wherein prior to the filling the space, the method further comprises:

forming interconnects between bond pads located on the second major surface of the semiconductor die and a second major surface of the second semiconductor die.

9. A method for forming a packaged semiconductor device, comprising:

attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a die pad of a lead frame, wherein no bond pads are located on the first major surface, wherein a top surface of each protrusion has a die attach material, wherein the die attach material directly contacts the first major surface and the top surface of each protrusion, and wherein the attaching results in a space under exposed portions of the first major surface of the semiconductor die between the plurality of protrusions;

forming wire bonds between bond pads located on a second major surface of the semiconductor die and fingers of the lead frame subsequent to the attaching, wherein the second major surface is opposite the first major surface; and

surrounding the semiconductor die with an encapsulant material that fills the space under the semiconductor die and is formed over the semiconductor die and the wire bonds subsequent to the forming the wire bonds, wherein the encapsulant material contacts the second major surface of the semiconductor die and contacts the first major surface of the semiconductor die between protrusions of the plurality of protrusions.

10. The method of claim 9 , wherein no curing is performed after the attaching the first major surface of the semiconductor die to the plurality of protrusions and before the forming the wire bonds.

11. The method of claim 9 , wherein the die attach material comprises a pressure sensitive adhesive.

12. The method of claim 9 , wherein top surfaces of the plurality of protrusions are not in a same plane as top surfaces of the fingers of the lead frame.

13. The method of claim 9 , wherein prior to the surrounding the semiconductor die with the encapsulant material, the fingers of the lead frame are separated from the die pad of the lead frame by a spacing; and wherein subsequent to the surrounding the semiconductor die with the encapsulant material, the encapsulant material fills the spacing.

14. The method of claim 9 , wherein each finger of the lead frame includes a bonding area for attachment of a wire bond.

15. The method of claim 9 , wherein a major surface of the die pad of the lead frame and a major surface of each finger of the lead frame are located in a same plane.

16. The method of claim 9 , wherein edges of the semiconductor die form a die perimeter, and wherein all external connections formed by the fingers of the lead frame are located outside of the die perimeter.

17. The method of claim 9 , wherein a total surface area of the top surfaces of the plurality of protrusions is at least one third a surface area of the semiconductor die.

18. The method of claim 9 , wherein the die attach material has sufficient adhesion to attach the semiconductor die to the plurality of protrusions while withstanding forces present during the forming wire bonds.

19. The method of claim 9 , wherein the plurality of protrusions extend from a top surface of the die pad, and the space is further defined as between the top surface of the die pad and the exposed portions of the first major surface of the semiconductor die.

Assignments (13)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 041414/0883 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNMENT DOCUMENTATION - INITIAL CONVENYANCE LISTED CHANGE OF NAME. PREVIOUSLY RECORDED ON REEL 040579 FRAME 0827. ASSIGNOR(S) HEREBY CONFIRMS THE UPDATE CONVEYANCE TO MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Dec 15, 2016
From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)
To: NXP USA, INC.
Reel/Frame 040945/0252 →
CHANGE OF NAME Recorded Nov 16, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040626/0683 →
CHANGE OF NAME Recorded Nov 9, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040579/0827 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0535 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 5, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037444/0444 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037358/0001 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035034/0019 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0923 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Feb 18, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 035033/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2014
From: SINGH, AKHILESH K.; HEGDE, RAMA I.; LAKHERA, NISHANT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 034017/0484 →
Continuity (1)
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